Automated test content generator supports automated RISC-V integration

Partnering with fabless semiconductor company, SiFive, test suite synthesis tool specialist, Breker Verification Systems, has developed an automated test content generator for RISC-V system integration testing.

The RISC-V TrekApp is claimed to be the first solution to address the entire RISC-V system on chip (SoC) system integration problem, It targets complex verification challenges and increases coverage by executing unpredictable corner-case scenarios without the need for manually developed test content, says Breker. The TrekApp works with existing universal verification methodology (UVM) and SoC verification environments and does not require the user to learn the portable test and stimulus PSS hardware verification language, defined by Accellera, used to model verification intent.

“RISC-V excels in enabling new and innovative designs, creating verification opportunities for system integration,” said Adnan Hamid, president and CEO, Breker. The RISC-V TrekApp automates verification while allowing for the distinctiveness created by RISC-V, he added, to save hours of laborious test development while increasing coverage.

The RISC-V TrekApp was developed in co-operation with SiFive, which provides commercial RISC-V processor IP and silicon. It was validated first on SiFive processors. It is also in use by multiple processor developers to test the integration of their custom devices.

The TrekApp provides a complete system integration test for RISC-V processors using Test Suite Synthesis. A configurable test content generator for UVM and Software Driven Verification (SDV) environments, it targets a range of subsystem verification challenges that otherwise require months of manual test authoring. It enables users to integrate a compliant RISC-V processor onto an SoC platform and perform all necessary tests to ensure the platform is ready to run without the need to learn the PSS language.

Features include interrupt mechanism testing, modular instruction extension verification and links to multiple compliance test suites. A comprehensive full debug environment highlights tests that fail, including memory map and key register detail, and interfaces with common debuggers such as Synopsys’ Verdi® SoC Debug Platform for extended analysis.

SoC operational profiling is accomplished using the TrekApp by scheduling many multi-threaded tests together. This allows design performance and power analysis for an early indication of general design operation. Extensive coverage information reveals how much of the subsystem functionality was tested and permits coverage-directed test generation for high-impact verification.

RISC-V TrekApp results can be combined with general functional verification tests written in PSS, SystemVerilog, UVM, SystemC and C/C++ for a complete, cross-coverage test environment. It does not require knowledge of PSS, SystemVerilog or UVM languages and may be used in a fully automated fashion.

The RISC-V TrekApp can be used with other TrekApps such as Power Domain, Security and additional common SoC verification functions. It operates on all standard simulators, emulators, rapid prototyping systems and virtual platforms, as well as post-silicon validation environments.

A cache coherency test suite enables automated systematic testing of data consistency and cache state transitions across all caches (L1/L2/L3 snoop filters) for multi-core/multi-cluster designs with I/O coherent interfaces such as PCI Express. Integration with fabrics, memory controllers (DDR and HBM) are stress tested as are atomic and other special memory accesses. For instruction extension verification, verification tests can be written in PSS, SystemVerilog, UVM and/or C/C++. These tests can be easily amalgamated with the system integration test suite for complete, diverse scenario examination to confirm that no additional instructions will impair smooth operation of the SoC.

Breker’s RISC-V TrekApp is available now as part of the Breker Trek5 product suite.

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