AWR v16 Design Environment advances 5G development, Cadence says
Cross-platform interoperability in the AWR Design Environment Version 16 supports RF to millimeter wave (mmWave) IP integration. This allows heterogeneous development across Cadence’s Virtuoso design, Allegro PCB and IC package design platforms.
The V16 release also introduces seamless integration with the Clarity 3D Solver and Celsius Thermal Solver, for electrothermal performance analysis of large-scale and complex RF systems. The AWR Design Environment, including Microwave Office circuit design software, enables customers to efficiently design 5G wireless and connected systems for automotive, radar systems, and semiconductor technologies and get to market faster, claims Cadence. Platform and solver integration in the V16 release provides up to a 50 per cent reduction in turnaround time (TAT) compared to competing workflows, continued the company.
Platform interoperability is crucial to expediting RF integration and promoting engineering productivity. Seamlessly sharing design data among the AWR Design Environment, Virtuoso, and Allegro platforms eliminates any disconnect between RF design and manufacturing layout teams. It also saves engineering resources and reduces development schedules. Cadence reports that the customers using the V16 release and its deep electromagnetic (EM) and thermal embedded analyses, are seeing more than a three-fold reduction in TAT.
“To win today in the highly competitive 5G/wireless markets, customers are demanding solutions that enable complete and comprehensive RF workflows that don’t just start and stop at the chip but extend to the entire system,” said Vinod Kariat, corporate vice president of research and development at Cadence. “The RF workflow innovations enabled by the AWR Design Environment V16 release start with a foundational advance in the way design data and software IP are now shared and seamlessly transferred across products.”
The latest version includes Allegro integration to ensure manufacturing compatibility and RF integration with PCB and IC package design flows, Virtuoso integration via Microwave Office for RF front-end design IP combined with the Virtuoso Layout Suite for IC and module integration. It also enables EM analysis for design verification of large RF structures such as module packaging and phased-array feed networks (Clarity) and provides thermal analysis for monolithic microwave IC (MMIC) and PCB high-power RF applications (Celsius).
“Cadence platforms such as the AWR Design Environment, Allegro PCB/SiP, and Virtuoso RF with integrated EM solver technologies are critical to the development of our RF/mmWave MMIC, RFIC and multi-chip 2.5/3D packaging technology,” said Florian Herrault, group leader, Advanced Packaging Solutions at HRL Laboratories. “Our design team is very excited by the performance and productivity gains to be had through Cadence’s RF solutions. Having the ability to share RF IP created in Microwave Office with our IC, package and board teams is driving a significant reduction in our overall design time so we can deliver the highest quality products to market faster.”
