BERT validates high speed chips at 1.6Tbits per second
At DesignCon 2022, Keysight Technologies will introduce a 120G Baud (GBd) high performance bit error ratio test (BERT). The M8050A validates next-generation chip deployments up to 120 GBd for 1.6Tbit per second.
It has been designed to overcome the problems faced by digital development and senior validation engineers as they move 112Gbits per second per lane to 224Gbits per second per lane. It uses high signal integrity to enable more test margin and allows customers to move to next-generation 1.6Tbit designs.
Keysight’s M8050A BERT delivers ASIC technology designed by Keysight to optimise the design to the requirements of the instrument. According to Keysight this deep level of integration simplifies set up and delivers reliable verification of designs at all speed grades with the combination of 120GBd pattern generator, coupled with high signal integrity.
It also saves time and investment, said Keysight, by providing flexibility with license upgradeable hardware when test requirements change. Software extensions within the M8070B BERT system software open the application space to support upcoming technologies with full connection to automation software.
Using Keysight’s Infiniium 80GHz UXR oscilloscope as an acquisition-based error-analyser in combination with M8050A provides a BERT that supports non-return to zero (NRZ) and pulse amplitude modulation (PAM) 4, as well as PAM 6/8, which is likely to be required in 1.6Tbit environment, Keysight pointed out.
Keysight’s industry experts, coupled with a proven automation framework, deliver test consulting for the latest and emerging markets with close connection to standards bodies.
At DesignCon 2022 (Santa Clara Convention Center, California, USA from 5 to 7 April) Keysight Technologies will be exhibiting at stand 1039. Visitors can see its PathWave Design Software, including PathWave ADS Memory, the company’s PCI Express (PCIe) 6.0/5.0 Tx Test, a PCIe transmitter test designed to assist with increases in digital transmission speed and throughput, and its PCIe 6.0/5.0 Rx Test for signals up to 64G transfers per second with PCIe 6.0. For data centre connectivity, there will also be the 224G Rx Test, the 224G Tx Test and the 112G Forward Error Correction (FEC) and Impairment compliance test designed to integrate FEC constraints into physical design validation for 800GBASE devices and components.
For consumer electronics, Keysight will also highlight its USB4 and DisplayPort 2.0 expertise over a lossy, low-cost, passive cable.
Other highlights will be the Signal Integrity Analysis: Demonstrating insight into the transmission of digital data from the transmitter, through the channel interconnects, to the receiver for hyperscale data centre network topologies, and DDR5 memory simulation and test, with new measurement science performing DDR5 compliance on a simulated waveform for fast repeatable test and a data repository for quick result analysis and decision making.
