Cadence accelerates constraints signoff

Described as the fastest path to full-chip constraints and clock domain crossing (CDC) signoff, Conformal Litmus has been introduced by Cadence to reduce overall design cycle times and enhance the quality of silicon in complex system on chip (SoC) designs.

The Conformal Litmus provides designers with 100 per cent signoff timer accuracy, says Cadence, and up to 10 times faster turnaround time compared with the previous generation solution.

This generation offers what is believed to be the industry’s first signoff static timer integration. This allows the Conformal Litmus to accurately model the design and the constraints using the same interpretation as the Tempus timing signoff solution, providing customers with 100 per cent signoff accuracy at the register-transfer level (RTL), claims Cadence.

CDC structural signoff verifies the structural correctness of CDC in the design from early RTL through to implementation flows. Smart analysis and reporting features provide rapid signoff capabilities. This can save weeks and even months in the design schedule, notes Cadence.

Checks for correctness and completeness of constraints at the block level are performed by the constraints signoff feature. This lets users perform hierarchical block versus top consistency checks at the SoC integration level. The Conformal Litmus smart analysis generates accurate, low-noise reports that shorten debug time and helps users achieve signoff-quality constraints rapidly.

Using multi-CPU parallelisation, provides verification across multiple cores, delivering up to 10 times faster turnaround time on SoC designs.

The Conformal Litmus is part of the Cadence digital and signoff portfolio for predictability and a faster path to design closure. It supports Cadence’s Intelligent System Design strategy for SoC design.

Hideyuki Okabe, director, Digital Design Technology Department, Shared R&D EDA Division, IoT and Infrastructure Business Unit, Renesas found: “With the Cadence Conformal Litmus solution’s multi-CPU parallelisation capabilities, we are able to complete runs on designs as large as 50M instances in under 10 hours. . . we expect to tape out with minimal iterations on quality of timing constraints between our design and implementation teams.”

“ The IP and ASICs we develop have extremely complex CDC structures, including handshake synchronisers, bus synchronisers and FIFOs,” said – Vikram Kuralla, director of engineering, Invecas. “CDC signoff tends to be cumbersome, since often the engineer entrusted with CDC verification has no knowledge of the design intent. The Cadence Conformal Litmus, after performing comprehensive analysis, presents the results in a very intuitive way. All insights required to understand the CDC intent and also timing constraints checks at RTL are readily available. This helps us rapidly sign off and effectively saves significant time in the schedule.”

“After evaluating the Cadence Conformal Litmus, we were impressed with its CDC capabilities, especially the smart analysis and reporting,” confirms Susumu Abe, general manager, Semiconductor IP & R&D Unit, Processor Development Department at NSITEXE. “This will enable us to quickly identify missing, invalid and incorrect CDC synchronization schemes in our designs. With the intuitive diagnosis capabilities, we expect that it will significantly accelerate our CDC signoff process,” he added.

Cadence’s software, hardware and semiconductor IP are used by customers to deliver products to market faster. The company’s Intelligent System Design strategy helps customers develop differentiated products—from chips to boards to intelligent systems—in markets as diverse as mobile, consumer, cloud data centre, automotive, aerospace, IoT and industrial segments.

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