Cadence demonstrates IP test silicon for PCI Express 6.0  

Cadence IP supporting the PCI Express (PCIe) 6.0 specification on the TSMC N5 process is now available. The Cadence IP for PCIe 6.0 consists of a DSP-based PHY and companion controller to deliver the optimised performance and throughput for applications such as hyperscale computing and 5G communications, including networking, emerging memory and storage. 

Early adopters of Cadence IP for PCIe 6.0 can access design kits now.

The 5nm PCIe 6.0 PHY test chip silicon demonstrated “excellent electrical performance” across all PCIe rates, reports the company. It was also reported that the PAM4/NRZ dual-mode transmitter delivered optimal signal integrity, symmetry and linearity with extremely low jitter. The DSP-based receiver demonstrated robust data recovery capabilities while withstanding harsh signal impairments and channel loss in excess of 35dB at 64G transactions per second. To contribute to reliability, the DSP core in the PHY provides continuous background adaptation to monitor and compensate for the signal fluctuations induced by environmental factors.

The controller IP for PCIe 6.0 is designed to provide the highest link throughput and utilisation while operating with extremely low latency. The highly scalable multi-packet processing architecture supports up to 1024-bit wide data path in x16 configuration while operating at 1GHz to achieve maximum aggregate bandwidth of 128Gbits per second. The feature-rich controller IP supports all new PCIe 6.0 features, including PAM4 signalling, forward error correction (FEC), FLIT encoding and L0p power state and retains backwards compatibility.

A PCIe 6.0 subsystem test chip was taped out on TSMC N5 in July. The subsystem test chip integrated the second generation power, performance and area (PPA)-optimised PCIe 6.0 PHY together with the PCIe 6.0 controller. The subsystem test chip enables Cadence to validate PCIe 6.0 PHY and controller functions at the system level and perform rigorous compliance and stress tests to ensure universal interoperability and reliability.

The Cadence IP for the PCIe 6.0 specification supports the company’s Intelligent System Design strategy. Cadence’s portfolio of design IP for TSMC’s advanced processes also includes 112G, 56G, die-to-die (D2D) and advanced memory IP solutions.

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