Cadence supports USB4 with first Verification IP

To support for the next-generation USB standard, Cadence Design Systems has announced availability of Verification IP (VIP) to enable early adoption of the protocol.

Believed to be the industry’s first, the Cadence VIP for USB4 enables engineers to develop standard-compliant system on chip (SoC) designs and complete functional verification of the design with less effort and greater assurance that the SoC will operate as expected, says Cadence.

The company is an active member of the USB Implementers Forum (USB-IF) and provides VIP and tools for developers to design to the newest USB standards.

Paul Cunningham, corporate vice president and general manager of the System & Verification Group at Cadence, said: “By offering the first-to-market VIP for USB4 as part of the Cadence Verification Suite, we’re enabling early adopters to ensure their advanced designs for mobile, consumer and display applications comply with the specification while achieving IP verification closure.”

The USB Promoter Group announced the pending release of the USB4 specification, based on Intel’s Thunderbolt protocol earlier this month. It enhances the transfer of both video and data, while doubling total available throughput to 40Gbits per second. Cadence developed the new USB4 VIP based on more than a year of collaborative work with early adopters of the specification. This collaboration has led to the availability of a proven and mature VIP that reduces design risks and shortens the implementation of the new standard, explains Cadence.

The Cadence VIP for USB4 includes TripleCheck technology, which provides a verification plan that is linked to the specification and a comprehensive test suite to ensure compliance with the USB4 specification.

Cadence VIP for USB4 is part of the Cadence Verification Suite which is comprised of best-in-class core engines, verification fabric technologies and solutions for design across a variety of applications and vertical segments.

Cadence software, hardware and semiconductor IP are used by customers to deliver products to market faster. The System Design Enablement strategy helps customers develop differentiated products—from chips to boards to systems—in mobile, consumer, cloud data centre, automotive, aerospace, IoT and industrial markets.

http://www.cadence.com