Cerebus automates chip design with machine learning
Machine learning (ML) technology is used in the Cerebus Intelligent Chip Explorer to drive the Cadence register transfer level (RTL) to increase productivity. Cerebrus uses ML technology to drive the Cadence RTL-to-signoff implementation flow, delivering up to 10 times productivity and 20 per cent power performance area (PPA) improvements for implementation.
The Cadence Cerebrus Intelligent Chip Explorer, a new machine learning (ML)-based tool that automates and scales digital chip design, enabling customers to efficiently achieve demanding chip design goals. The combination of Cerebrus and the Cadence RTL-to-signoff flow offers advanced chip designers, CAD teams and IP developers the ability to improve engineering productivity by up to 10X versus a manual approach while also realizing up to a 20% better power, performance and area (PPA).
The Cerebrus tool is cloud-enabled and utilises scalable compute resources from cloud providers to rapidly meet design requirements across a range of markets including consumer, hyperscale computing, 5G communications, automotive and mobile.
The tool includes reinforcement ML, which quickly finds flow solutions human engineers might not naturally try or explore, improving PPA and productivity, says Cadence. There is also ML model reuse, which allows design learnings to be automatically applied to future designs, reducing the time to better results.
Another feature is improved productivity where a single engineer can optimise the complete RTL-to-GDS flow automatically for many blocks concurrently. Massively distributed computing provides scalable on-premises or cloud-based design exploration for faster flow optimisation.
There is also a powerful user cockpit interface which allows interactive results analytics and run management to gain valuable insights into design metrics.
“Previously, design teams didn’t have an automated way to reuse historical design knowledge, leading to excess time spent on manual re-learning with each new project and lost margins,” said Dr. Chin-Chi Teng, senior vice president and general manager in the Digital & Signoff Group at Cadence. Cerebus allows engineering teams to offload manual processes as the industry continues to move to advanced nodes and design size and complexity increase, explains Cadence and allows designers to achieve PPA goals much more efficiently.
Cerebrus is part of the broader Cadence digital full flow, working seamlessly with the Genus Synthesis Solution, Innovus Implementation System, Tempus Timing Signoff Solution, Joules RTL Power Solution, Voltus IC Power Integrity Solution and Pegasus Verification System to provide customers with a fast path to design closure and better predictability. The tool and broader flow support the company’s Intelligent System Design strategy.
