Codasip announces add-ons to Western Digital’s RISC-V ISA core

Three commercially licensed add-ons to the Western Digital SweRV Core EH1 are available from RISC-V processor IP specialist, Codasip. The add-ons enable the 32-bit, dual-issue, RISC-V ISA core to be designed into a wider range of applications.

SweRV Core EH1 has a nine-stage pipeline, open-sourced through the CHIPS (Common Hardware for Interfaces, Processors and Systems) Alliance. The three options available from Codasip are a floating point unit (FPU), a data cache and additional instructions for bit manipulation.

The FPU supports the RISC-V single precision and double precision instructions. The data cache has configurable size, associativity, and cache lines. It can be configured with either AXI or AHB-Lite interfaces. Thirdly, the additional instructions for bit manipulation can be beneficial for error detection/error correction, digital signal processing (DSP), and security algorithms.

“The development of business models around open-source processor cores is following a similar path to the software world,” explained Codasip’s CEO, Karel Masařík. He likened the three options to the SweRV Core EH1 as similar to the commercially licensed add-ons to open-source software, such as IBM’s database software and middleware, which are offered as paid options to Linux. The three adds-on will be available on a similar basis, he said.

The SweRV Core EH1 is a powerful, two-way superscalar, 32-bit embedded processor core with a nine-stage pipeline. It was developed by Western Digital; the company also developed the EH2 and EL2 cores. All three cores were deployed with commercial EDA tools and software development kit, supported by Codasip’s SweRV Core Support Package Pro.  A free version is available through the CHIPS Alliance on GitHub.

The EH1 has an optional four-way set-associative instruction cache and optional instruction and data closely-coupled memories.

The SweRV Core EH1, EH2, and EL2 are available to the open-source community through the CHIPS Alliance. The open-source development organisation seeks to provide a barrier-free environment to allow collaboration for open-source software and hardware code.

Codasip delivers RISC-V processor IP and high-level processor design tools to IC designers, providing the advantages of the RISC-V open ISA, and the ability to customise the processor IP. As a founding member of the RISC-V Foundation and a long-term supplier of LLVM and GNU-based processor solutions, Codasip is committed to open standards for embedded and application processors.

The company was formed in 2014 and is headquartered in Munich, Germany, Codasip has R&D centres in Europe and sales representatives worldwide.

Picture credit: iStock, DKosig

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