Codasip boosts studio processor design tools with AXI automation 

Further enhancements to Codasip’s Studio processor design toolset has resulted in Studio 9.1 which includes an expanded bus support with full AXI for high-performance designs, as well as improved support for both LLVM and code density.

Studio works with designers to custom make the RISC-V processor from a Codasip embedded or application core design. With Studio 9.1, users can gain access to additional bus interfaces to include full AXI which means Studio will support the development of more powerful application cores and multi-core systems. 

Codasip’s latest update incorporates the LLVM-based SDK (the fast C/C++ compiler, Linker support package – all of which were incorporated as part of Studio 9.0 launched in April 2021. This update helps improve support for custom instructions in application cores running a rich OS, such as GNU/Linux. Another new feature brings support for ISA sub-targets that reduce the maintenance of different SDKs for different ISA configurations. 

Zdenek Prikryl, Codasip CTO, said: “We are constantly evolving our tools offering and due to the nature of the diverse customer types, our projects and developments continue to help push our design tools further. Codasip is keen to simplify design for differentiation with our processor cores and tools which we have developed to make it easy for designers of any size to benefit from enabling them to get high-performance, cost-effective and significantly differentiated products to market quickly and easily.”

As a founding member of RISC-V International and a long-term supplier of LLVM and GNU-based processor solutions, Codasip is committed to open standards for embedded and application processors. Formed in 2014 and headquartered in Munich, Germany, Codasip currently has research & development centres in Europe and sales representatives worldwide. 

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