Codasip partners with Western Digital to support open source RISC-V
Configurable RISC-V embedded processor IP supplier, Codasip has partnered with Western Digital to become the preferred provider of hardware implementation packages and expert technical support for users of Western Digital’s SweRV Core EH1. The SweRV Core EH1 RISC-V core is currently available to the open source community and supported by the open source development organisation, the CHIPS Alliance, which allows collaboration for open-source software and hardware code.
The SweRV Core EH1 is a 32-bit, two-way superscalar, nine-stage pipeline core introduced earlier this year by Western Digital. It has a performance of 4.9 CoreMark/MHz and a small footprint, making it suitable for embedded devices supporting data-intensive edge applications, such as storage controllers, industrial IoT, real-time analytics in surveillance systems and other smart systems. The power-efficient design also offers clock speeds of up to 1.8GHz on a 28nm CMOS process technology.
The new SweRV support package (SSP) from Codasip provides all of the components necessary to design, implement, test, and write software for a SweRV Core-based SoC, including but not limited to verification test benches and IP, reference scripts for EDA flows, models for simulation and emulation and software development tools. The offering is backed by professional technical support.
“Users can confidently implement the SweRV Core into their chip at a fraction of the cost of competing technologies,” said Karel Masařík, CEO of Codasip. “By offering this service, we hope to contribute significantly to companies that are turning to open IP to innovate within their next semiconductor device. Also, we plan to continue development of the SweRV Core under the CHIPS Alliance organisation.”
Zvonimir Bandić, senior director of next generation platforms architecture at Western Digital, said: “By teaming up with Codasip, we make it even easier to transition to RISC-V and further expand the potential for innovation that brings computing power closer to data.”
The SweRV Core EH1 is part of the RISC-V portfolio by Western Digital and is available through the CHIPS Alliance, a project hosted by the Linux Foundation for the creation and deployment of open SoCs, peripherals and software tools for mobile, computing, consumer electronics, and Internet of Things (IoT) applications.
The SSP, along with optional professional technical support services, will be available for licensing in Q1 2020 directly from Codasip.
