Compiler can accelerate 2.5D and 3D designs
A single, unified 3DIC platform enables system-driven PPA per cubic mm silicon optimisation, says Synopsys. Complex SoCs for compute-intensive applications such as high-performance computing, AI and 5G, can manage 2.5D and 3D designs now that its 3DIC compiler has been qualified for Samsung Foundry’s Multi-Die Integration (MDI) flow.
The unified 2.5D and 3D multi-die package co-design and co-analysis platform allows mutual customers to manage the complexities of 2.5D and 3D designs, while benefiting from power, performance and area (PPA) advantages and scalability to support hundreds of billions of transistors via a single 3DIC platform.
The two companies say they are easing the way to optimised multi-die designs through early to full system implementation and signoff analysis, said Sangyun Kim, vice president of Foundry Design Technology Team at Samsung Electronics. “Co-design and co-analysis of silicon and advanced packages with Synopsys’ 3DIC Compiler platform is another example of how our close collaboration results in advanced productivity solutions that reduce turnaround time and costs for our mutual customers,” he said.
Multi-die integration, in which many chip dies are stacked and integrated in a single package, are growing in popularity as a means to meet system specifications in terms of PPA, functionality, form factor and cost. They provide end-product modularity and flexibility to mix and match separate technologies addressing different market segments or needs. The 3DIC Compiler is built on the common, scalable data model of the integrated Synopsys Fusion Design Platform, and enables multi-die integration co-design and co-analysis to provide a single, hyper-convergent environment for 3D visualisation, pathfinding, exploration, design, implementation, analysis and sign off.
“The 3D workflow has traditionally been extremely fragmented and iterative, with multiple tools and flows needed to achieve multi-die system integration, thus limiting engineering productivity,” said Shankar Krishnamoorthy, general manager and corporate staff for the Silicon Realization Group at Synopsys.
“Samsung and Synopsys have worked closely to validate 3DIC Compiler for the foundry’s MDI flow, providing our mutual customers with a tapeout-proven platform to optimize their innovative multi-die designs and get to market quickly,” he added.
The 3DIC Compiler platform integrates multi-die, extraction and static timing analysis (STA) with StarRC and PrimeTime golden-sign off solutions; electromigration / IR drop (EMIR), signal integrity / power integrity (SI / PI) and thermal analysis with Ansys RedHawk-SC and HFSS technologies, circuit simulation with PrimeSim Continuum; IC Validator design rule checking (DRC) and layout versus schematic (LVS); and Synopsys TestMAX IEEE1838 multi-die design-for-test (DFT) solution.
3DIC Compiler is part of the broader Fusion Design Platform and, combined with Fusion Compiler, enables expansive, multi-die, RTL-to-GDSII co-optimisation. There is also DesignWare Foundation, 112G USR/XSR Die-to-Die and HBM2/2E/3 IP, SiliconMAX In-Chip Monitoring and Sensing IP and support for integrated photonics. There is hardware and software co-verification, power analysis and system physical prototyping with the Synopsys Verification Continuum platform.
