Customisable RISC-V IP cores is fully customisable, says Semidynamics
Claimed to be the first fully customisable 64-bit RISC-V family of cores to be able to handle the large amounts of data required for AI, machine learning and high performance computing (HPC), cores released by Semidynamics are process agnostic. Versions are available down to 5nm.
Customers can control the configuration, said Semidynamics, rather than having, configurations fixed by the vendor or with a limited number of configurable options such as cache size, address bus size, interfaces and a few other control parameters. The IP cores available from Semidynamics enable the customer to have control over the configuration, in terms of new instructions, separate address spaces or new memory accessing capabilities . “This means that we can precisely tailor a core to meet each project’s needs so there are no unrequired overheads or compromises,” said Roger Espasa, CEO and founder of Semidynamics. “Even more importantly, we can implement a customer’s ‘secret sauce’ features into the RTL in a matter of weeks,” he added.
The first core, the Atrevido, is available for licensing now. It has out-of-order scheduling that is combined with the company’s proprietary Gazzillion technology. The core can handle highly sparse data with long latencies and with high bandwidth memory systems, typically found in today’s machine learning applications. According to Semidynamics, Gazzillion technology removes the latency issues that can occur when using CXL technology to enable far away memory to be accessed at supercharged rates.
The Gazzillion technology is specifically designed for recommendation systems that are a key part of data centre machine learning processes. By supporting over a hundred misses per core, an SoC design can deliver sparse data to the compute engines without a large silicon investment. In addition, the core can be configured from two- for four-way versions to help accelerate the not-so-parallel portions of recommendation systems.
For the most demanding workloads, such as HPC, the Atrevido core supports large memory capacities with its 64-bit native data path and 48-bit physical address paths. According to Espasa, these are the fastest cores on the market for moving large amounts of data with a cache line per clock at high frequencies “even when the data does not fit in the cache. And we can do that at frequencies up to 2.4Hz on the right node” making them suitable for applications streaming a lot of data and/or if the application touches very large data that does not fit in cache. Competing core IPs average one cache line over many cycles, he added.
MMU support means Atrevido is also Linux-ready including supporting cache-coherent, multi-processing environments from two to hundreds of cores. It is vector ready, supporting both the RISC-V Vector Specification 1.0 as well as the upcoming Semidynamics Open Vector interface. Vector instructions densely encode large numbers of computations to reduce the energy used by each operation. Vector Gather instructions support sparse tensor weights efficiently to help with machine learning workloads.
Espasa concluded, “No-one else has such a complex RISC-V core that can be totally configured to perfectly meet the specific needs of each project rather than having to use an off-the-shelf core and compromise.”