Delivering support for advanced packaging technologies
Cadence Design Systems’ digital tools and advanced IC packaging solutions now support the new TSMC InFO_MS (InFO with memory on substrate) packaging technology.
Support for this TSMC packaging technology enables customers of both companies to create new, complex chips using 3D stacking techniques to bring innovative new products to market much faster, claims Cadence.
Cadence says its flexible suite of advanced packaging solutions will be beneficial to customers designing chips of various sizes and levels of complexity with memory integrated on InFO. The signoff and packaging solutions incorporate several capabilities to make it easy to use TSMC’s InFO_MS packaging technology.
Tools include the Quantus Extraction Solution, Voltus-Sigrity Package Analysis Solution, Tempus Timing Signoff Solution, Physical Verification System, OrbitIO Interconnect Designer, Cadence System-in-Package, Layout Enhancements and Sigrity PowerSI technology, Sigrity PowerSI 3D-EM extraction option, Sigrity PowerDC technology, Sigrity XtractIM technology and Sigrity SystemSI technology.
“Cadence has continued to partner with TSMC to deliver new capabilities in support of its advanced packaging technologies that allow customers to deliver innovative designs more efficiently,” said Tom Beckley, senior vice- president and general manager, custom IC and PCB group, Cadence.
“The new InFO_MS solution can empower our mutual customers to use the latest packaging techniques when creating complex designs, and we are committed to enabling them to achieve their design objectives using our tools, flows and methodologies,” he said.
Suk Lee, TSMC senior director, design infrastructure marketing division, said: “The collaboration with Cadence on the InFO_MS design flow enriches our established InFO, WoW and CoWoS chip integration solutions, giving customers more flexibility to incorporate multiple die integration using 3D stacking techniques.
“Our ongoing collaboration with Cadence is enabling customers to use our packaging technologies effectively so they can reduce design schedules and achieve aggressive design goals.”
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Photo credit: TSMC
