Design and test combination reduces development time for DDR5 memory

At DesignCon 2020 (28 to 30 January), Keysight Technologies, will unveil what is believed to be the world’s first design and test workflow solution that reduces product development time for double-data rate (DDR5) DRAM systems.

DDR5 DRAM is needed as data centre throughput climbs, driving the need for high density, fast memory in servers. It runs at twice the data rate of DDR4 to shrink design margins, reports Keysight. As a result it becomes difficult for a hardware designer to optimise the PCB to minimise the effects of jitter, reflection and crosstalk. Heavily distorted signals can be recovered with decision feedback equalisation (DFE), a new addition for DDR5 DRAM, which disrupts the traditional measurement and simulation approaches used for earlier generations of DDR.

Keysight’s design and test workflow enables hardware engineers to meet their time-to-market window and deliver a high-performance, reliable end-product, says the company.

The design and test workflow solution consists of the W2225BP for modelling and simulation, probes and interposers, transmitter test with oscilloscopes and compliance software (Infiniium UXR, N6475A), receiver test fixtures, a receiver test solution for loopback BER testing (M8020A, M80885RCA), the U4164A or B4661A for logic analysis and the N7-24A power rail probes.

It has new transmitter test methods to measure the signal eye diagram after equalisation, new loopback bit-error-rate (BER) receiver tests to validate device and system reliability and logic analysis to debug complex DDR5 traffic transactions to identify the source of system instability.

Completing the solution is PathWave ADS Memory Designer for DDR5, a simulation environment. It has the ability to predict performance, optimise a design and perform virtual transmitter compliance test, before realising the first hardware prototype. It also reduces simulation setup time from hours to minutes with new features such as DDR components, smart wires and an intelligent memory probe.

Increased simulation accuracy for DDR5 is achieved by representing receiver equalisation with IBIS algorithmic modelling interface (IBIS-AMI) models, reports Keysight, which have been enhanced specifically for the requirements of DDR.

DesignCon is held at Santa Clara Convention Center, Santa Clara, California USA from 28 to 30 January. Visit Keysight Technologies at booth 725.

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