Design IP addresses PAM4 SerDes for AI/ML SoC design

DSP-based, multi-rate SerDes IP, optimised for power, performance and area for 5G and artificial intelligence/machine learning (AI/ML) SoC design has been added to the Design IP portfolio by Cadence Design Systems.

The 56G long-reach SerDes IP is on TSMC’s N7 and N6 process technologies and addresses hyperscale computing, cloud data centre and optical networking applications, as well 5G infrastructure deployment in baseband and remote radio head systems. It is now part of Cadence’s PAM4 SerDes portfolio.

The Cadence 56G long-reach SerDes IP supports the Cadence Intelligent System Design strategy for customers developing 5G, compute server processor and ML workload-accelerator SoC design enablement.

It is claimed to offer designers best-in-class 36db+ insertion loss using Cadence’s multi-rate DSP technology and an industrial temperature range, CPRI data rate support and per-lane PLL for 5G applications.

It has achieved 56G long-reach performance on N7 test silicon and is compatible with the N6 process and is compliant with the IEEE standard specification.

Power configurations are programmed via a firmware-controlled adaptive power optimiser, for optimal power-performance trade offs and more efficient system designs based on platform requirements, said Cadence.

The Cadence 56G long-reach SerDes IP also includes optimal data recovery through the programmable DSP-based architecture, which is claimed to allow optimal power delivery for a given reach and data recovery under lossy and noisy channel conditions.

The extended reach capability allows customers to use lower cost PCBs and achieve greater flexibility in PCB and system design, added Cadence.

“After being first to market in 2019 with silicon-proven 112G-LR SerDes on TSMC 7nm technology, we have now expanded our offering to include PPA-optimised 56G-LR to address the connectivity needs of the 5G infrastructure and AI/ML market. This new PAM4-based 56G-LR SerDes is based on Cadence’s well-proven multi-rate DSP technology,” said Rishi Chugh, vice president of product marketing, IP Group at Cadence. “The availability of Cadence’s 56G long-reach SerDes IP on the TSMC N7 and N6 processes accelerates the adoption and deployment of cost-effective 100G and 400G networks.”

Cadence provides electronic design and applies its Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality.

Cadence customers are innovative companies, delivering electronic products from chips to boards to systems for the most dynamic market applications including consumer, hyperscale computing, 5G communications, automotive, aerospace, industrial and health.

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