DSP processor IP has wide vector architecture for parallel operations

To accelerate parallel automotive, sensor fusion and communications applications, Synopsys has announced DesignWare ARC VPX5 and VPX5FS DSP processors, based on an extended instruction set and very long instruction word/single instruction-multiple data ((VLIW/SIMD) architecture.

Synopsys explains that the DesignWare ARC VPX5 DSP and VPX5FS DSP processor IP is based on an extended ARCv2DSP instruction set and optimised for  high-performance signal processing applications, such as radar/lidar, sensor fusion and baseband communications processing. The VLIW/SIMD architecture combines scalar and vector execution units to enable a high degree of parallel processing, adds Synopsys.

The ARC VPX5FS DSP offers safety monitors, lockstep capabilities and other hardware safety features that help designers achieve the most stringent levels of functional safety and fault coverage without significant impact on power or performance, claims the company.

The ARC VPX5 and VPX5FS processors support single-, dual-, and quad-core configurations.  Each VPX core contains a scalar execution unit and multiple vector computation units that support 8-bit, 16-bit, and 32-bit SIMD computations within a 512-bit vector word. The DSPs are configurable; designs can be optimised for power and area by selecting only the hardware features and vector resources needed to meet the required performance level. Neural network algorithms used in machine learning (ML) and artificial intelligence (AI) applications can be efficiently processed by the ARC VPX processors using the 8-bit data type, as well as 16-bit and 32-bit floating point data types, confirm Synopsys.

To address the growing use of floating-point calculations in complex DSP algorithms, up to three vector floating point pipelines are available in each core. The ARC VPX5 and VPX5FS support half-, single-, and double-precision floating point data types. Each VPX core also provides dedicated hardware acceleration for linear algebra and math instructions, delivering ultra-high performance for equation-based computations. The ARC VPX DSP processors can deliver 512FLOPs and 32-math operations per cycle.

Both DSPs are supported by the ARC MetaWare development toolkit with optimising C/C++ compiler. An auto-vectorisation capability enables the compiler to efficiently map all supported floating point and non-floating-point data types onto the respective SIMD execution units with full MAC unit saturation. The compiler is able to efficiently map VLIW operations to all vector computation units, enabling highly parallel execution, says Synopsys.

The Synopsys DesignWare ARC VPX5 processor is expected to be available to lead customers in Q1 2020. The Synopsys DesignWare ARC VPX5FS processor is expected to be available to lead customers in Q2 2020.


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