Efabless democratises chip creation with a carrier chip and open source design
A programme of a pre-designed carrier chip and automated open source design flow from Efabless brings chip creation to the masses, says the company. Its chipIgnite programme has been launched in collaboration with SkyWater Technology. The initiative removes access barriers by significantly reducing cost and the need for deep semiconductor experience to design chips, says the company.
The chipIgnite programme expands upon SkyWater Technology’s SKY130-based open source chip manufacturing program sponsored by Google and supports private commercial designs that include non-open source IP.
The chipIgnite programme includes low-cost manufacturing, but also a development board and firmware stack to simplify design validation and test. All projects created as part of the chipIgnite programme will use a full chip reference design template that implements the physical I/O for the chip as well as provides a common management area to support test and evaluation of the user’s design. There is also an optional automated open source design flow for implementing projects that enables users to generate layouts for their digital projects from RTL. The chipIgnite programme will provide users a guaranteed reservation to ensure their project is included, says eFabless.
SkyWater’s open source 130nm CMOS platform will be used to fabricate chips for the chipIgnite programme. The automotive-grade, mixed-signal platform is suited to IoT and edge computing to combine digital and analogue circuit performance with embedded non-volatile memory for a range of SoC architectures. The programme provides users 10mm2 of total project area with fabrication for projects using the SkyWater Open Source process design kit (PDK).
The chipIgnite programme builds on a community of over 1500 users for the Open PDK initiative where new designers can get support and access to resources through community messaging platforms such as Slack. In addition to using freely-available design flows based on open source EDA tools, designers can use proprietary design tools to address design requirements not supported by open source tools.
The programme targets users who want to create an initial prototype or proof-of-concept for an IP block or full SoC. The starting price of $9750 per project includes 100 QFN or 300 WCSP packaged parts and five evaluation boards. The chipIgnite shuttles also support users who are distributing initial boards or launching a pilot for a product. An option for 1000 WCSP parts at $20 each is available that enables the service to be used for early product builds.
The first manufacturing run is optimised for university digital and mixed-signal chip design courses with a submission deadline for tapeout of June 18, 2021. The delivery of parts and assembled boards is planned for early October.
The first shuttle in the chipIgnite programme will support fabrication of student projects as part of the EE272B course in the Electrical Engineering department at Stanford University for senior undergraduate and graduate students.
chipIgnite is supported by QuickLogic and the CHIPS Alliance.
