Enclustra develops module with 38.4-Gbyte per second bandwidth

Based on the Xilinx Zynq UltraScale+ high memory bandwidth MPSoC module, Enclustra’s Mercury+ XU9 SoC module offers 20 multi-gigabit transceivers with data rates of up to 15-Gbit/sec each.

The Mercury+ XU9 combines six Arm cores, a Mali-400MP2 GPU (EV variant), up to 12-Gbyte DDR4 SDRAM, a number of standard interfaces, 192 user I/Os and up to 504,000 LUT4 equivalents.

The Mercury+ XU9 MPSoC module is FPGA specialist Enclustra’s sixth SOM family based on the Zynq UltraScale+ MPSoC. It has two memory banks – a 64-bit wide DDR4 SDRAM (up to 4-Gbytes) connected to the PL and a 72-bit DDR4 ECC SDRAM (up to 8-Gbytes) connected to the PS to create a wide memory bandwidth of up to 38.4-Gbytes per second.

To transport the data to be processed into and out of the module quickly, 20 multi-gigabit transceivers, each with a data transmission rate of up to 15Gbit per second are available.

In addition to the usual standard interfaces such as two Gigabit Ethernet and USB 3.0 ports, dedicated interfaces like DisplayPort, SATA, as well as SGMII are available on the 74 × 54mm module.

The Mercury+ XU9 is also populated with a 16-GByte eMMC and a 64-MByte QSPI Flash. Both the processing system and the FPGA matrix have PCIe connections.

The Xilinx Zynq UltraScale+ MPSoC is manufactured in a 16nm FinFET+ process and has six Arm cores, namely four 64-bit Arm Cortex-A53 with a clock frequency of up to 1,333MHz and a 533MHz fast 32-bit Arm dual core Cortex-R5. The processors are supported by a Mali-400MP2 graphics processor unit (GPU) and a H.264/H.265 video codec (EV variants).

Enclustra recommends using the Mercury + XU9 with the Mercury+ PE1-300 or Mercury+ PE1-400 base boards for development and prototyping.

The Mercury+ PE1 base board is a complete development platform, supplied with detailed documentation and reference designs, user manual, user schematics, a 3D-model, PCB footprints and differential I/O length tables.

The Enclustra Build Environment can be used to compile Linux for the Enclustra SoC modules with integrated Arm processors. The module and base board are selected by a graphical interface before the Enclustra Build Environment downloads the appropriate Bitstream, first stage boot loader (FSBL) and the required source code. Finally, U-Boot, Linux and the root file system based on BusyBox are compiled.


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