Entry level RZ/V2L microprocessors handle AI inference and image processing
Claimed to have best-in-class power efficiency, the RZ/V2L microprocessors from Renesas incorporate its Dynamically Reconfigurable Processor artificial intelligence accelerator (DRP-AI) designed to make embedded AI more power efficient.
DRP-AI handles both AI inference and image processing functions, eliminating external image signal processor (ISP) requirements.
The latest additions to the RZ/V series of microprocessors are designed for entry level, AI-enabled applications.
The new RZ/V2L shares the high-precision AI inference capabilities combined with power efficiency of the previous RZ/V2M series. Additionally, it includes optimisations such as tailoring the DRP-AI operating frequency and memory interface for an entry-level microprocessor.
The DRP-AI provides both real time AI inference and image processing functions with the capabilities essential for camera support such as colour correction and noise reduction. This enables customers to develop AI-based vision applications, such as point-of-sale (PoS) terminals and robot vacuum cleaners, without requiring an external image signal processor (ISP). The power efficiency eliminates the need for heat dissipation measures such as heat sinks or cooling fans. According to Renesas, the RZ/V2L means AI can be implemented cost-efficiently not only in surveillance cameras and industrial equipment, but also in a range of applications including home appliances and consumer electronics.
The RZ/V2L is also package- and pin-compatible with the existing RZ/G2L general-purpose microprocessors from Renesas. This allows RZ/G2L users to upgrade to the RZ/V2L for additional AI functions without needing to modify the system configuration. This helps to keep migration costs low.
The entry level AI accelerator products allow customers to select the most suitable product from Renesas’ microprocessor range.
As part of the RZ/V2L development environment, Renesas offers the complimentary DRP-AI Translator, which automatically converts AI models into an executable format. The input format is the industry-standard Open Neural Network Exchange (ONNX). Developers can leverage the DRP-AI while using the tools they are accustomed to, allowing them to immediately start using the RZ/V2L to evaluate AI models based on proven learning data.
The RZ/V2L microprocessors feature a 64-bit Arm Cortex-A55 (1.2GHz, dual or single core) and Cortex-M33 processor with DRP-AI (1Terra operations per second per W) AI accelerator capable of running the Tiny YOLOv2 program at 28 frames per second.
Simple ISP functions required for machine vision are provided in the DRP library. There is also a 16-bit, single-channel DDR memory interface, 3D graphics functions via an Arm Mali-G31 graphics processor unit (GPU), video codec (H.264) and CMOS sensor interfaces (MIPI-CSI and Parallel) for camera input. There are also MIPI-DSI and parallel display interfaces and error checking and correction (ECC).
A Verified Linux Package (VLP) based on Civil Infrastructure Platform Linux is standard with an industrial-grade Linux implementation also available.
The RZ/V2L series is available in 15mm or 21mm square BGA packages that are pin-compatible with the RZ/G2L
RZ/V2L evaluation boards are provided as Smart Mobility ARChitecture (SMARC) system on modules (SoMs). The reference designs provide an optimised circuit diagram and board layout, and include a power supply circuit and timing tree. A power management IC (PMIC) optimised for the RZ/V2L is in development, confirms Renesas and solutions incorporating the RZ/V2L and new PMIC are expected to be available in the second half of 2021.
Sample shipments of the RZ/V2L start today, and mass production is scheduled to begin in December 2021.