eSilicon announces production of FinFET ASIC for 5G infrastructure

A large 2.5D FinFET ASIC targeting the 5G infrastructure market is entering final product qualification, announces eSilicon. The company has collaborated with the ASE Group for packaging, Rambus for the high-performance SerDes, Samsung for the 14nm FinFET ASIC fabrication and HBM memory stacks and UMC for the silicon interposer.

The design, which is over 600mm2, contains multiple HBM2 memory stacks on a silicon interposer, employs over 100 lanes of SerDes and contains over 800Mbit of embedded SRAM.

“Designs of this size require specialised analysis and materials, so collaboration between ecosystem players has become more crucial than ever,” said Calvin Cheung, vice president of engineering at ASE Group.

“Rambus’ high performance and flexible SerDes technology, with a large number of SerDes lanes running at various speeds, is a key enabler for this complex ASIC,” said Hemant Dhulla, vice president and general manager of IP cores at Rambus. “We are excited to collaborate with our ecosystem partners on the strategic elements to drive the next-generation 5G network growth.”

“This is one of the largest dies we have produced in this 14nm node,” said Hong Hao, senior vice president of Foundry Marketing at Samsung Semiconductor.

Pablo Temprano, Samsung Semiconductor’s vice president of memory marketing added: “The 5G market will mark a new era of technological efficiency for which this 2.5D FinFET ASIC is set to help lead the way.”

“Many 5G designs will require 2.5D technology with a silicon interposer,” said Walter Ng, vice president of sales at UMC. “UMC’s technology provides a critical enabler for these designs.”

Ajay Lalwani, vice president of global manufacturing operations at eSilicon, explained: “Getting this design into production was a real team effort between eSilicon and our ecosystem partners. This teamwork, and the resultant success of this complex part in the end system is the new definition of ASIC success.”

eSilicon provides complex FinFET ASICs, market-specific IP platforms and advanced 2.5D packaging solutions. Its ASIC-proven, differentiating IP includes highly configurable 7nm 56G/112G SerDes plus networking-optimised 16, 14 or 7nm FinFET IP platforms featuring HBM2 PHY, TCAM, specialised memory compilers and I/O libraries. eSilicon’s neuASIC platform provides AI-specific IP and a modular design methodology to create adaptable, highly efficient AI ASICs. eSilicon serves the high-bandwidth networking, high-performance computing, AI and 5G infrastructure markets.

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