Ethernet PHY family “doubles router and switch capacities”

According to Alan Weckel, founder and technology analyst at 650 Group, the industry’s transition to a 112G PAM4 serial ecosystem for high-density routers and switches, mean that line-rate encryption and efficient use of port capacity become increasingly important. Microchip’s META-DX2+ Ethernet PHYs will enable MACsec and IPsec encryption, optimising port capacity with port aggregation and flexibly connect routing/switching silicon to multi-rate 400G and 800G optics, he said.

The PHYs are claimed to be the industry’s first product to integrate 1.6Tbits per second of line rate end-to-end encryption and port aggregation. They maintain a compact footprint during the transition to 112G PAM4 connectivity and meet demand for increased bandwidth and security in network infrastructure, led by AI / ML (machine learning) applications and the transition to 112G PAM4 connectivity beyond just cloud data centre and telecomms service provider switches and routers to enterprise Ethernet switching platforms. 

The company has announced four META-DX2+ Ethernet PHYs powered by its Meta-DX retimer and PHY portfolio.

“By offering both hardware and software footprint compatibility, our customers can leverage architectural designs across their enterprise, data centre, and service provider switching and routing systems that can offer pay-as-you-need enablement of advanced features including end-to-end security, multi-rate port aggregation, and precision timestamping via software subscription model,” said Babak Samimi, corporate vice president of Microchip’s communications business unit.

META-DX2+’s configurable 1.6T data path architecture outperforms the next near competitors by a factor of two in total gearbox capacity, claimed Microchip, with hitless 2:1 protection switch mux modes enabled by its ShiftIO capability. The flexible XpandIO port aggregation capabilities optimise router / switch port utilisation when supporting low-rate traffic.  

The PHYs also include IEEE 1588 Class C/D Precision Time Protocol (PTP) support for nanosecond timestamping required for 5G and enterprise business critical services. 

Microchip said that by offering a portfolio of footprint-compatible retimer and advanced PHYs with encryption options, it enables developers to expand their designs to add MACsec and IPsec based on a common board design and software development kit (SDK). 

META-DX2+ differentiated capabilities include dual 800 GbE, quad 400 GbE and 16x 100 / 50 / 25 / 10 / 1 GbE MAC / PHY. The integrated 1.6T MACsec / IPsec engines offload encryption from packet processors so systems can more easily scale up to higher bandwidths with end-to-end security, explained Microchip.

XpandIO enables port aggregation of low-rate Ethernet clients over higher speed Ethernet interfaces, optimised for enterprise platforms, while the ShiftIO feature, and configurable integrated crosspoint enable flexible connectivity between external switches, processors and optics.

There is support for Ethernet, OTN, Fibre Channel and proprietary data rates for AI / ML applications.

Device variants are available with 48 or 32 Long Reach (LR) capable 112G PAM4 SerDes including programmability to optimise power versus performance.

According to Microchip more than 20 per cent board savings can be realised, compared to competing solutions that require two devices to deliver the same 1.6T gearbox and hitless 2:1 mux modes.

The META-DX2+ PHYs can be used with Microchip’s PolarFire FPGAs, the ZL30632 high-performance PLL, oscillators, voltage regulators, and other components that have been pre-validated as a system to help speed designs into production.

Microchip’s second-generation Ethernet PHY software development kit for the META-DX2 family lowers development costs with field-proven API libraries and firmware. It supports all META-DX2L and META-DX2+ PHY devices within the product family. Support for the Open Compute Project (OCP) Switch Abstraction Interface (SAI) PHY extensions are included.

The META-DX2+ family is expected to sample during Q4 2022.

Microchip will be exhibiting the META-DX2L PHY device, at the Optical Internetworking Forum (OIF) booth at the European Conference on Optical Communication (ECOC) September 18-22, 2022, in Basel Switzerland.

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