Evolution of PCIe® Standards and Test Requirements
Designers of data center systems and devices face ever-increasing demands to provide faster speeds. Ethernet network interfaces in data centres are moving to speeds of
400 gigabits per second (Gb/s) and will likely double in the coming years. PeripheralComponent Interconnect Express (PCIe) 5.0, the latest iteration of the standard, will
enable the mass adoption of 400 gigabit Ethernet (GE) technologies in the data centre. PCIe is a core technology used in many types of computer servers and endpoint
devices. The PCI Special Interest Group (PCI-SIG®) defines specifications and compliance tests that guarantee the interoperability of PCIe systems. PCIe 5.0
provides full-duplex bandwidth of approximately 128 gigabytes per second (GB/s) for a 16-lane system.
The PCIe standard has evolved from PCIe 1.0, released in 2003 supporting 2.5 gigatransfers per second (GT/s), to PCIe 5.0, released in 2019 supporting 32 GT/s.
PCIe is scalable, and slots come in different configurations of bidirectional lanes: x1, x4, x8, x16, x32. The number represents the number of lanes in the PCIe slot. For
example, a PCIe x1 slot provides one lane and transmits data at 1 bit per cycle. A PCIe x2 slot provides two lanes and transmits data at 2 bits per cycle, and so on.
PCIe cards fit interchangeably into slots, but the bandwidth available depends upon the version of the PCIe standard of the card.
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