First IP for PCI Express 6.0 has low latency for HPC and AI
IP that supports the latest features in the PCI Express (PCIe) 6.0 specification has been released by Synopsys. The DesignWare IP can be used for early SoC development, high performance computing and artificial intelligence (AI).
The IP for PCIe 6.0 includes controller, PHY and verification IP, for early development of PCIe 6.0 SoCs. It supports the latest features in the standard specification including, 64 GT/s PAM-4 signalling, FLIT mode and L0p power state. Acccording to Synopsys the IP addresses evolving latency, bandwidth and power-efficiency requirements of high performance computing (HPC), AI and storage SoCs.
To achieve the lowest latency with maximum throughput for all transfer sizes, the DesignWare Controller for PCI Express 6.0 uses a MultiStream architecture, delivering up to x2 the performance of a single-stream design. The controller, with available 1024bit architecture, allows designers to achieve 64Gtransfers per second x16 bandwidth and closing timing of 1GHz. The controller provides optimal flow with multiple data sources and in multi-virtual channel implementations. To facilitate accelerated testbench development with built-in verification plan, sequences and functional coverage, the VC Verification IP for PCIe uses native SystemVerilog/UVM architecture that can be integrated, configured and customised.
Synopsys’ DesignWare PHY IP for PCIe 6.0 provides adaptive DSP algorithms that optimise analogue and digital equalisation to maximise power efficiency regardless of the channel. The PHY enables near zero link downtime using patent-pending diagnostic features. The placement-aware architecture of the DesignWare PHY IP for PCIe 6.0 minimises package crosstalk and allows dense SoC integration for x16 links, added Synopsys. The datapath is optimised with ADC-based architecture for low latency.
The DesignWare Controller and PHY IP for PCIe 6.0 early access are scheduled to be available in Q3 of 2021. The Verification IP for PCIe 6.0 is available now.
Synopsys develops silicon-proven IP for SoC designs. The DesignWare IP portfolio includes logic libraries, embedded memories, PVT sensors, embedded test, analogue IP, wired and wireless interface IP, security IP, embedded processors and sub-systems. Synopsys’ IP Accelerated initiative offers IP prototyping kits, IP software development kits and IP subsystems accelerate prototyping, software development and integration of IP into SoCs. The company’s invests in IP quality, comprehensive technical support and robust IP development methodology to enable designers to reduce integration risk and accelerate time-to-market.
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