Framos develops IP core and evaluation board for Xilinx FPGAs

Imaging and vision technology specialist, Framos, has developed the SLVS-EC (scalable low voltage signalling with embedded clock) RX IP core and evaluation board for sensor interfacing with Xilinx FPGAs.

The proprietary FPGA module available with an evaluation board, connects Sony’s latest high-speed SLVS-EC interface with Xilinx FPGAs. Vision engineers can seamlessly upgrade to Sony’s interface technology, announces Framos.

Sony’s new high-speed interface standard SLVS-EC is one of the future image sensor interface benchmarks with up to eight lanes providing 2.3Gbit per seconds each, for three to four times higher bandwidths, higher resolutions or a simplified system design comparing to SubLVDS, explains Framos. The RX IP core reduces overhead and complexity implementing a Sony imager with SLVS-EC. As on-chip function block connecting the customer’s FPGA logic with the image sensor’s data stream, the IP core receives the interface data, manages the byte-to-pixel conversion for various lane configurations and prepares an efficient processing workflow run by the FPGA.

The Framos software will support SLVS-EC v1.2 with one, two, four, or eight lanes configurable by the user and delivers pixels formats from eight- to 14-bit of raw data. By de-risking the sensor implementation the IP coret significantly reduces the development efforts and accelerates the time to market, claims Framos.  

The Framos SLVS-EC RX IP core is believed to be the first solution for Xilinx FPGAs on the market. Framos is an official Xilinx partner, and the companies work in close co-operation. The SLVS-EC RX IP core will work with the main existing and upcoming FPGA families. The package includes the encrypted RTL IP core with a simulation environment (ModelSim) and dedicated reference implementation examples. The evaluation board will provide designs to guide and test the implementation of a SLVS-EC-based sensor, including the hardware/software environment and documented implementation examples with sources.

Users can benefit from faster sensors with an increased performance, using the IP core, in addition to a simplified and smaller hardware design by using less lanes, says Framos. With the embedded clock, the interface is robust against clock-skew, allowing larger bandwidth and making dedicated clock lanes obsolete.

The SLVS-EC RX IP core will be released mid-May, 2018.

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