Free reference model is released with updates for riscvOVPsimPlus

Simulation technology and a reference model is available, free of charge, from Imperas Software. The offering includes test suites for basic processor hardware verification and compliance testing.

The company specialises in RISC-V processor verification technology. It has announced updates to riscvOVPsimPlus with support for the near-ratified P extension and architectural validation test suites. The P (or packed SIMD/DSP) extension is a significant addition to the flexibility of the modular RISC-V instruction set architecture (ISA), says Imperas. It supports real-time data processing applications as part of the main processor pipeline without the need for the associated inefficiencies of a co-processor. For processor hardware verification, a basic test suite provides a basic software level compatibility to the new P extension as a reference to the developers’ interpretation of the written specification.

riscvOVPsimPlus is a free instruction set simulator (ISS) that is an envelope model that can be configured to cover all of the ratified RISC-V specifications and standard extensions. It includes architectural validation test suites, which form a basic test plan for software level compatibility within the specification definitions. The Imperas models are available as open source and licensed under the Apache 2.0 flexible open source license. All models, virtual platforms and example models are provided to the community via the Open Virtual Platforms website Imperas offers simulation technology and products based on the freely available open standard public OVP application programming interfaces (APIs).

The Imperas RISC-V architectural validation test suites are collections of tests focused on specific ISA extensions that provide basic testing of instruction execution and usage of the full range of operands with a set of representative data values. Although not a substitute for full tests suites for design verification, they provide detailed coverage reports of the different parts of the architectural specification tested. The currently released test suites available free on the OVP website now include P‑SIMD/DSP, K-crypto, V-vector, B-bitmanip, F, D, I, M, and C.

“By combining SIMD/DSP functionality within the RISC-V ISA offers the ideal balance for performance, flexibility and efficiency,” said Wei Wu, PLCT Lab, ISCAS, vice-chair of RISC-V International P Extension Task Group. The Imperas RISC-V reference model is intended as a starting point to explore and develop software algorithms based on the new RISC-V P extension, according to the company.

“RISC-V is changing the design process as new design exploration can start without many of the traditional barriers. The adoption of riscvOVPsimPlus with the new RISC-V P extension support helps provide clarification of the specification boundary as a useful guideline for innovation in new processor designs,” said Simon Davidmann, CEO at Imperas Software.

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