IAR Embedded Workbench to support RISC-V P extension
Following a partnership with Andes Technology, a Premier founding member of RISC-V, IAR Systems has announced initial support for the draft RISC-V P extension in IAR Embedded Workbench for RISC-V.
The RISC-V International is in the process of standardising a series of extensions beyond the integer base instructions which can be implemented or omitted as desired depending on the design goals (for example energy / area / performance / storage goals). The RISC-V P extension is designed to be a standard extension for Packed-SIMD instructions. It targets efficient media processing for audio, voice and images, and is a generalisation of a Packed-SIMD extension donated to the RISC-V International by Andes Technology.
“We have achieved around 9x performance boost of CIFAR-10 inference with RISC-V P extensions. Packed-SIMD provides edge processors more computing power with higher energy efficiency and minimal increase in cost, and such capability empowers edge devices to deal with voice and slow video processing,” commented Dr Chuanhua Chang, the chair of RISC-V P extension Task Group and head of architecture at Andes Technology.
“Anders Holmberg, general manager, embedded development tools, IAR Systems, added: “By jointly supporting the P extension, we bring extended possibilities for powerful RISC-V development and add new ways to optimise application and hardware performance.”
RISC-V is a free and open instruction set architecture (ISA) based on established reduced instruction set computing (RISC) principles. Launched in 2019, IAR Embedded Workbench for RISC-V provides optimisation for application and on-board memory. It also enables companies to add functionality to an existing platform. To ensure code quality, the toolchain includes C-STAT for integrated static code analysis. C-STAT can help prove compliance with specific standards like MISRA C:2004, MISRA C++:2008 and MISRA C:2012, as well as detect defects, bugs, and security vulnerabilities as defined by the Common Weakness Enumeration (CWE) and a subset of CERT C/C++.
The current version of IAR Embedded Workbench for RISC-V provides support for RV32 and RV32E 32-bit RISC-V cores and extensions. Future releases will include 64-bit support, as well as functional safety certification and security solutions.
