IAR Systems provides toolchain for RISC-V
A C/C++ compiler and debugger toolchain from IAR Systems, Embedded Workbench for RISC-V has support for RISC-V cores.
Optimisation technology in IAR Embedded Workbench helps developers ensure the application fits the required needs and optimise the utilisation of on-board memory. Companies can also add functionality to an existing platform. Internal tests show that the first version of the IAR C/C++ Compiler for RISC-V architecture delivers “major improvements in code density, generating code that is considerably smaller compared to code generated by other available tools”.
The toolchain includes C-STAT for integrated static code analysis. It can also be used to prove compliance with specific standards like MISRA C:2004, MISRA C++:2008 and MISRA C:2012, as well as detect defects, bugs, and security vulnerabilities as defined by the Common Weakness Enumeration (CWE) and a subset of CERT C/C++.
The IAR Embedded Workbench includes the C-SPY Debugger which gives full control of the application in real-time, and its simulator provides full debugging capabilities even without access to the hardware. For in-circuit debugging, IAR Systems provides the probe I-jet for a high-speed debugging platform with full code control.
A growing number of companies are adopting the RISC-V architecture and IAR Systems says its position in the RISC-V ecosystem enables it to provide worldwide technical support.
“The addition of IAR Embedded Workbench to the RISC-V ecosystem will further push the RISC-V adoption across the embedded industry.” says Calista Redmond, CEO, RISC-V Foundation. “IAR Systems provides development tools for users all over the world, and I’m excited to witness the company’s compiler technology, static code analysis and extensive debug functionality brought to the RISC-V community.”
RISC-V is a free and open instruction set architecture (ISA) based on established reduced instruction set computing (RISC) principles.
The first version of IAR Embedded Workbench for RISC-V provides support for RV32 32-bit RISC-V cores and extensions. Future releases will include 64-bit support and support for the smaller RV32E base instruction set, as well as functional safety certification and security solutions.