Jitter attenuators by Silicon Labs are ready for 5G networks
A fully integrated reference is offered for the Si539x jitter cleaners by Silicon Labs. According to the company, this enhances system reliability and performance while simplifying PCB layout in high-speed networking designs.
The Si539x jitter attenuators are purpose-built to address the reference clock requirements of 100, 200, 400, 600 or 800G designs, providing more than 40 per cent margin to the stringent jitter requirements of 56G PAM-4 SerDes used in Ethernet switch system on chips (SoCs), PHYs, FPGAs and ASICs. This also provides future-proofing for emerging 112G SerDes designs, says Silicon Labs.
Network equipment providers need to develop higher speed, higher capacity gear capable of handling 5G wireless traffic, which is driving the need for higher performance timing solutions for fronthaul/backhaul, metro/core and data centre applications, explained James Wilson, general manager of Timing Products at Silicon Labs. He continued: “FPGAs and PHYs with integrated 56Gbits per second SerDes enable higher capacity 100/200/400/600/800G optical and Ethernet line cards but face increasingly complex circuit board design and layout challenges”.
The Si539x jitter attenuators integrate a reliable crystal, tested over temperature and pre-screened for activity dips.
The Si539x devices have been qualified over a range of reliability tests including shock, vibration, temperature cycling and crystal aging. The tightly specified crystal and innovative device construction reduce crystal sensitivity to temperature changes caused by system fans, leading to more consistent, reliable operation, adds Silicon Labs.
The integrated reference device construction provides higher immunity to acoustic emissions (AE) than external crystal-based designs. AE is the radiation of noise waves that occurs when a PCB is subject to temperature gradients or external mechanical forces that cause micro-cracks or plastic deformation in the PCB assembly. The Si539x’s package construction isolates and protects the crystal from AE noise, explains Silicon Labs.
To save space on high-port-count optical and Ethernet line cards, the jitter attenuator, with an integrated reference, can minimise the PCB footprint by more than 35 per cent. An integrated reference also eliminates the need for the keep-out area under the crystal, enabling denser clock routing around the device, further simplifying PCB layout.
Si539x devices generate any combination of frequencies from 100Hz to 1028MHz on up to 12 differential clock outputs, eliminating the need for standalone clock generators and clock buffers to enable clock-tree-on-a-chip clocking while eliminating the additive jitter associated with discrete clock tree solutions.
Samples and production quantities of the new Si539x jitter attenuators are available now. There is also a range of evaluation boards for Si539x devices with internal or external references. They work seamlessly with ClockBuilder Pro, to develop custom configurations and measure performance.