Libero SoC design suite v12.0 delivers productivity gains for FPGA design

The latest version of Libero SoC delivers significant productivity gains while marking major production milestones for the low-power PolarFire FPGA family, claims Microchip Technology.

To meet the increased complexity and resource use in each generation of FPGA designs, Microchip, via its Microsemi subsidiary explains that Libero SoC version 12.0 delivers new gains in runtime and quality of results, as well as one unified design suite for all of the company’s latest-generation FPGA families, including new production releases of PolarFire FPGAs.

Libero SoC v12.0 reduces design flow runtimes and, with the improved quality of results, it provides results in fewer design iterations and improves customer productivity, says the company. By upgrading to Libero SoC v12.0, designers will see runtime reduction of 60 per cent for timing, 25 per cent for place and route and 18 per cent for power results. They will also see an average increase of four per cent in quality of results for larger designs and a 10 per cent improvement for the PolarFire MPF300/TS-1 device, claims Microchip.

Libero SoC v12.0 is being released simultaneously with the production release of the PolarFire MPF100T, PolarFire MPF200T and PolarFire MPF300T devices. The release includes production timing and power for PolarFire MPF300T-1 devices, as well as support for two devices for the aerospace and defence markets. The low-power, radiation-tolerant RT4G150L, which offers 25 per cent savings for standard speed grade, and military-grade support for the SmartFusion2 M2S150T/S FCV484 device.

Microchip explains the benefits of a unified design suite for PolarFire, IGLOO2, SmartFusion2 and RTG4 FPGAs as eliminating the need to qualify multiple pieces of software when working across product families. Libero SoC v12.0 now supports FPGA Hardware Breakpoint (FHB) for RTG4 and PolarFire devices, PCIe debug support for PolarFire and continuous transceiver eye monitoring using SmartDebug.

The new release also improves double date rate (DDR) memory performance by an average of 29 per cent in high-effort mode and 39 per cent in regular-effort mode. Enhanced Tool Command Language (TCL) support enables customers to run the entire design flow on the command line if desired.

Microchip’s Libero SoC v12.0 design suite is available now to support customers designing with its PolarFire, IGLOO 2, SmartFusion 2 and RTG4 FPGAs.

https://www.microsemi.com