Linting tool supports automatic conversion for Microchip and SoC FPGAs
Mixed HDL language simulation and hardware-assisted verification company, Aldec, has updated its Alint-Pro linting tool to enhance the support of Microchip Technology’s Libero SoC design suite. The new release supports automatic conversion of Libero projects into Alint-Pro’s environment for static linting and clock domain crossing (CDC) analysis of hardware designs in VHDL, Verilog or SystemVerilog.
Static linting helps detect a variety of design issues, including poor coding styles, improper clock and reset management, simulation versus synthesis mismatches, incorrectly implemented finite state machines (FSM), and other typical source code issues throughout the design flow. CDC analysis is critical to designs with multiple asynchronous clocks and helps mitigate non-deterministic issues such as data incoherence as a result of metastability that inevitably appear in today’s large FPGA and SoC FPGA designs.
“The use of advanced verification tools such as static linting and CDC analysis can significantly reduce the number of non-trivial bugs escaping into production, save engineering resource and more importantly, increase the reliability of FPGA and SoC FPGA designs,” said Louie De Luna, Aldec’s director of marketing. The company has been a Microchip FPGA partner since 1987.
“FPGA designs are increasing in size and complexity requiring earlier detection of language and structural errors”, said Joe Mallett, senior marketing manager at Microchip. “Designers using Libero SoC Design Suite can take advantage of Aldec’s Alint-Pro to help detect functional errors earlier in the FPGA design cycle.”
ALINT-PRO 2022.12 is available now for download and evaluation.
Alint-Pro is a design verification solution for RTL code written in VHDL, Verilog, and SystemVerilog. It is focused on verifying coding style and naming conventions, RTL and post-synthesis simulation mismatches, smooth and optimal synthesis, correct FSM descriptions, clock and reset tree issues, CDC, RDC, DFT, and coding for portability and reuse.
It performs static analysis based on RTL and SDC source files, uncovering critical design issues early in the design cycle which, in turn, reduces design sign off time dramatically. Running Alint-Pro before the RTL simulation and logic synthesis phases prevents design issues spreading into the downstream stages of design flow and reduces the number of iterations required to finish the design.
Established in 1984, Aldec specialises in electronic design verification and offers a patented technology suite including: RTL design, RTL simulators, hardware-assisted verification, SoC and ASIC prototyping, design rule checking, CDC verification, IP cores, high performance computing (HPC) platforms, embedded development systems, requirements lifecycle management, DO-254 functional verification and military/aerospace solutions.