Low-power PCI Express Gen 4 buffers simplify clock distribution
Buffers in the Si532xx family are the first to deliver PCIe Gen 4-compliant 1.5/1.8V applications, says Silicon Labs. The Gen 1/2/3/4 clock buffers provide low jitter clock distribution in 1.5 and 1.8V applications. With additive jitter performance of 40fs RMS (typical), the Si532xx PCIe clock buffers provide more than 90 per cent margin to stringent PCIe Gen 3 and Gen 4 jitter specifications, simplifying clock distribution, says the company and reducing risk on product development.
Data centre hardware designs including network interface cards (NICs), PCIe bus expanders and high-performance computing (HPC) accelerators are increasingly using low-power 1.5 or 1.8V supplies to minimise overall power consumption. Powered from a single 1.5 to 1.8V supply and featuring up to 12 clock outputs, the Si532xx buffers can provide low-jitter PCIe clock distribution in low-power designs. The Si532xx clocks support PCIe common clock, separate reference no spread (SRNS) and separate reference independent spread (SRIS) architectures, enabling them to be used in a variety of applications. The Si532xx clocks are non-PLL-based fan-out buffers, supporting the distribution of spread spectrum clock signals without impacting signal integrity. As the number of PCIe endpoints continues to expand in server and storage applications, system designers need to buffer more copies of the PCIe reference clock. The Si532xx family’s low jitter performance enables designers to cascade multiple buffers while still meeting the maximum allowable system PCIe jitter budget of 0.5ps RMS.
Output drivers leverage Silicon Labs’ push-pull HCSL technology, which eliminates the need for external termination resistors required by conventional PCIe buffers using constant-current output driver technology. Internal power filtering prevents power supply noise from degrading clock jitter performance, eliminating discrete low-dropout regulators. The Si532xx family supports both 85 and 100-Ohm impedance options. Silicon Labs offers PCIe Gen 1/2/3/4 software that simplifies PCIe jitter measurements. This can be downloaded from the learning center section of the Silicon Labs’ website.
Samples and production quantities of the Si532xx PCIe clock buffers are available now in multiple output options. The Si53212, Si53208 and Si53204 clocks provide twelve, eight and four PCIe clock outputs. Samples ship in two weeks, and production quantities are available in four weeks.
Silicon Labs’ Si53204-EVB development kit provides quick, simple PCIe buffer evaluation.