Mentor repositions IC design with Tessent streaming scan network
Demand for next-generation ICs that deliver the performance required for evolving applications such as AI and autonomous driving has resulted in an unprecedented increase in the size of IC designs, says Mentor. They can integrate billions of transistors. To help IC engineering teams test these larger IC designs without time penalties and to address the engineering effort to plan for and deploy design for test (DFT) structures and functionalities across each design, Mentor has introduced Tesset.
The Tessent Streaming Scan Network software is for Mentor’s Tessent TestKompress software. It includes embedded infrastructure and automation that decouples core-level DFT requirements from the chip-level test delivery resources. This enables a bottom-up DFT flow that can dramatically simplify DFT planning and implementation, while reducing test time up to a factor of four. It has full support for tiled designs and optimisation for identical cores, making it particularly suitable for increasingly large compute architectures.
“The dramatic spike in IC test complexity due to increasing design sizes, advanced technology nodes, and use-model requirements presents significant challenges for IC design organisations,” said Brady Benware, vice president and general manager of Tessent Silicon Lifecycle Solutions for Mentor, a Siemens business. “With the Tessent Streaming Scan Network, our customers can be ready for the designs of tomorrow, while slashing test implementation effort and simultaneously optimising manufacturing test cost today,” he said.
Tessent Streaming Scan Network is a bus-based scan data distribution architecture that enables simultaneous testing of any number of cores. It helps shorten test time by enabling high speed data distribution, efficiently handling imbalances between cores, and supporting testing of any number of identical cores with a constant cost. It also provides an interface in each core that simplifies scan timing closure and is suitable for abutted tiles, advises Mentor.
There is a series of host nodes in each design block, which are networked together. Each host distributes data between the network and the test structures in the block. The software automates the implementation, pattern generation, and failure reverse mapping processes. DFT engineers can optimise DFT test resources for each block without having to worry about impacts to the rest of the design, reducing the implementation effort. Other features to reduce test data time and volume are optimised handling of identical cores, elimination of waste in the test data, and time multiplexing.
The software is already used by Samsung. “With the support for Tessent Streaming Scan Network technology in Tessent TestKompress, we are able to offer our customers a scalable test access solution ideal for today’s and tomorrow’s advanced IC designs,” said Sangyun Kim, vice president of Design Technology Team at Samsung Electronics. “We have found that the Tessent Streaming Scan Network significantly reduces the effort needed to make complex designs highly testable.”
Tessent Streaming Scan Network is compatible with all other Tessent DFT products and can be combined with Tessent Diagnosis cell-aware and layout-aware diagnosis for a complete end-to-end defect detection and diagnosis solution.
All Tessent DFT products are part of the Tessent Safe ecosystem and qualified for all ASIL ISO 26262 projects with a complete set of certified ISO 26262 documentation.
