Microchip claims clock buffers are first to meet DB2000Q/QL standards

Four 20-output differential clock buffers that exceed PCIe Gen 5 jitter standards for next-generation data centre applications have been released by Microchip.

The ZL40292 (85 Ohm termination) and ZL40293 (100 Ohm termination) are specifically designed to meet the new DB2000Q specification and the ZL40294 (85 Ohm termination) and ZL40295 (100 Ohm termination) are designed to meet the DB2000QL industry standard. All four devices also meet PCIe Gen 1, 2, 3 and 4 specifications.

Each buffer complements chipsets in PCIe applications where distributed clocks are required across several peripheral components, such as central processing units (CPUs), field programmable gate arrays (FPGAs) and physical layers (PHYs) in data centre servers and storage devices, for example. The devices’ low additive jitter of approximately 20 femto seconds exceeds the DB2000Q/QL specification of 80 femto seconds, points out Microchip. This provides designers large margins to meet tight timing budgets while achieving increasing data rates, continues the company. The clock buffers will minimise jitter when distributing clocks to up to 20 outputs, thereby maintaining the integrity and quality of the clock signal through the buffer.

The buffers achieve low power dissipation and contribute to power savings via low-power high-speed current steering logic (LP-HCSL). This consumes one third of the power of standard HCSL and also gives customers the ability to drive longer traces on the board, improving signal routing while reducing components and board space. The ZL40292, for example, can eliminate up to 80 termination resistors (four per output) compared to traditional HCSL buffers, reports Microchip.

The ZL40292 and ZL40293 are available now for sampling and in volume production in 72-pin 10 x 10mm QFN packages. The ZL40294 and ZL40295 are available now for sampling in the 80-pin 6.0 x 6.0 QFN packages.


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