Microchip delivers first RISC-V SoC FPGA for real-time Linux
At this week’s RISC-V Summit, Microchip, via its Microsemi subsidiary, announces an extension to its Mi-V ecosystem. It has released details of the architecture for a new class of SoC FPGAs, combining what is claimed to be the industry’s lowest power mid-range PolarFire FPGA family with a complete microprocessor sub-system based on the open, royalty-free RISC-V Instruction Set Architecture (ISA).
Microchip’s PolarFire SoC architecture brings real-time deterministic asymmetric multiprocessing (AMP) capability to Linux platforms in a multi-core coherent central processing unit (CPU) cluster. The PolarFire SoC architecture has been developed in collaboration with SiFive, and features a flexible 2Mbyte L2 memory subsystem that can be configured as a cache, scratchpad or a direct access memory. This allows designers to implement deterministic real-time embedded applications simultaneously with a rich operating system for a variety of thermal- and space-constrained applications in collaborative, networked IoT systems.
Embedded developers require the richness of Linux-based operating systems for the convergence of 5G, machine learning and the IoT. These must meet deterministic system requirements in ever lower power, thermally-constrained design environments, while addressing critical security and reliability requirements. Traditional SoC FPGAs blend reconfigurable hardware with Linux-capable processing on a single chip to provide developers with devices for customisation, can consume too much power, lack proven levels of security and reliability, or use inflexible and expensive processing architectures, reports Microchip.
PolarFire SoC includes extensive debug capabilities including instruction trace, 50 breakpoints, passive run-time configurable Advanced eXtensible Interface (AXI) bus monitors and FPGA fabric monitors, in addition to Microchip’s built-in two-channel logic analyser, SmartDebug.
The PolarFire SoC architecture includes single error correction and double error detection (SEC-DED) on all memories, physical memory protection, a differential power analysis (DPA) safe crypto core, defence-grade secure boot and 128kbit flash boot memory.
Polarfire SoC evaluation and design is supported by the antmicro Renode system modelling platform, which is now integrated with Microchip’s SoftConsole integrated design environment (IDE) for embedded designs targeting PolarFire SoCs. A PolarFire SoC development kit is also available. This consists of the PolarFire FPGA-enabled HiFive Unleashed expansion board and SiFive’s HiFive Unleashed development board with its RISC-V microprocessor subsystem.
Microchip is also launching a Mi-V Embedded Experts Program, a worldwide partner network to assist customers in hardware/software designs for PolarFire SoC. The programme ensures support throughout the entire lifecycle of customer products and helps to jump-start designs and shorten time to market, explains the company. Members also get access to direct technical support and early access to development platforms and silicon.
