Microchip introduces high level synthesis design suite for PolarFire FPGAs

One of the challenges around the popularity of FPGAs in edge computing is that the majority of edge compute, computer vision and industrial control algorithms are developed natively in C++ by developers with little or no knowledge of FPGA hardware. Microchip Technology has therefore developed the SmartHLS high level synthesis design workflow for its PolarFire FPGA families. The suite enhances productivity and ease of design by allowing C++ algorithms to be directly translated to FPGA-optimised register transfer level (RTL) code.

It enhances Microchip’s Libero SoC design tool suite to make the mid-range PolarFire and PolarFire SoC platforms accessible to algorithm developers without them having to become FPGA hardware experts, observed Bruce Weyer, vice president of Microchip’s FPGA business unit.

“Together with our VectorBlox Neural Network Software Development Kit these tools will greatly improve designers’ productivity in creating cutting-edge solutions using C/C++ based algorithms for applications such as embedded vision, machine learning, motor control and industrial automation using FPGA-based hardware accelerators.”

The SmartHLS design suite is based on the open source Eclipse integrated development environment (IDE) and uses C++ software code to generate a hardware description language intellectual property (HDL IP) component for integration into Microchip’s Libero SmartDesign projects. As a result, engineers can describe hardware behaviour at a higher level of abstraction than is possible with traditional FPGA RTL tools, said Microchip.

According to the company, it also improves productivity while reducing development time through a multi-threading application programming interface (API) that executes hardware instructions concurrently and simplifies the expression of complex hardware parallelism as compared to other HLS offerings.

The SmartHLS tool requires up to 10 times fewer lines of code than an equivalent RTL design, with the resulting code being easier to read, understand, test, debug and verify. The tool also simplifies exploration of hardware microarchitecture design trade-offs and enables a developer’s pre-existing C++ software implementations to now be used with PolarFire FPGAs and FPGA SoCs.

According to Microchip, its PolarFire FPGAs and FPGA SoCs offer the industry’s lowest power at mid-range densities. The company recently announced low-density additions to the family that consume half the static power of alternatives in what is claimed to be the world’s smallest thermal footprint, to reduce system costs and meet thermal management requirements without forfeiting bandwidth. These FPGAs,  as well as the company’s SmartFusion 2 FPGAs and IGLOO 2 FPGAs are also supported by the SmartHLS tool.

Developers can initiate designs now using the SmartHLS v2021.2 tool, available via the Microchip website. It is part of the Libero SoC V2021.2 design suite and can also be used as stand-alone software.


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