MIPS processor core prepares for advanced LTE/5G communications
Delivering 50 per cent higher performance in less than 20 per cent area increase than the previous generation of multi-threaded multi-core processor, MIPS has released the I7200 multi-threaded multi-core processor. MIPS describes it as a high performance licensable IP core in their mid-range 32-bit product line-up. Class-leading efficiency is essential to power sensitive applications such as the high bandwidth modem sub-systems in Advanced LTE Pro and upcoming 5G smartphone SoCs, as well as networking ICs, and other applications, says MIPS.
David Lau, MIPS’ vice president of engineering explained: “The performance gains across the board on the new I7200 deliver a leap forward in support of the transition to 5G systems, while providing a range of configurable features that enable the CPU core to be optimised for a specific application. For communications processing in LTE modems, where small size and power consumption are at a premium, and latency and deterministic responsiveness are critical to system performance, the I7200 can be tuned to optimise the characteristics for real-time embedded processing.”
Part of the MIPS 32-bit I-Class family of processor cores, the I7200 is built on MIPS’ multi-threading technology, which delivers higher levels of performance efficiently, says MIPS, but is a key mechanism supporting very low latency response to high priority events in real-time embedded systems. In addition to these characteristics, the I7200 has simultaneous multi-threading with thread prioritisation and zero cycle context switching. Other features that make the processor particularly suitable for the high performance and fast response to real-time events in embedded applications are configurable memory management, with options for full TLB-based MMU or simpler, deterministic 32 region memory protection unit (MPU). The I7200 also has tightly coupled, fast-access, deterministic ScratchPad RAMs (SPRAMs, up to 1Mbyte each) for instructions, data for each core, or unified implementations.
Complementing the focus for use in embedded real-time systems, the I7200 is the first MIPS core to use the nanoMIPS ISA, which delivers industry-leading small code size. nanoMIPS is a variable instruction length ISA consisting of 16, 32 or 48-bit instructions and other optimisations that complement goals of delivering performance in smallest code size. Using an equivalent compiler and compile flags the code size is up to 10 per cent smaller than alternative cores competing in similar applications, claims MIPS. This reduces the overall memory footprint for a system, and is essential for high performance communications and real-time embedded systems, as it maximises the amount of code that can be fit into the fastest, local RAM arrays for low latency, deterministic execution of high priority events and interrupts.
The production released version of the IP core is available immediately for licensing.