Multi-Die DesignWare includes low latency die-to-die controller IP

Based on low latency architecture to support AMBA CXS to interface with Arm Neoverse Coherent Mesh network, the DesignWare die-to-die controller IP complements the company’s 112G USR/XSR PHY IP for a complete die-to-die IP solution.

Designers can exploit the low-latency, high-bandwidth die-to-die connectivity to address the increased workload and faster data movement demands of high-performance computing (HPC), artificial intelligence (AI) and networking SoCs. The DesignWare Die-to-Die Controller and PHY IP are part of the Synopsys multi-die solution, consisting of HBM IP and 3DIC compiler, accelerating SoC designs requiring advanced packaging.

“Interconnect technology is increasingly vital for the next-generation of performant, customized infrastructure SoCs,” said Jeff Defilippi, director of product management, Infrastructure Line of Business, Arm. “With its low-latency, native support for AMBA CXS, Synopsys DesignWare die-to-die controller can integrate with the Arm Coherent Mesh Network to provide our mutual customers access to the multi-chip IP offering scale-up performance and composability options required for this next era of infrastructure compute,” he said.

The DesignWare die-to-die controller provides error recovery mechanisms such as optional forward-error correction and cyclic redundancy check for higher data integrity and link reliability. The DesignWare die-to-die controller’s flexible configuration supporting the AMBA CXS and AXI protocols allows coherent and non-coherent data communication for easy integration into Arm-based and other high-performance SoCs.

The controller has support for up to 1.8Tb/s PHY bandwidth addresses high-performance computing demands of SoCs requiring robust die-to-die connectivity.

“The trend of die splitting and disaggregation require ultra- and extra-short reach links to enable inter-die connectivity with high data rates,” explained John Koeter, senior vice president of marketing and strategy for IP at Synopsys.

Synopsys’ DesignWare IP portfolio includes logic libraries, embedded memories, IOs, PVT monitors, embedded test, analogue IP, interface IP, security IP, embedded processors and sub-systems. To accelerate prototyping, software development and integration of IP into SoCs, Synopsys’ IP Accelerated initiative offers IP prototyping kits, IP software development kits and IP subsystems.

The DesignWare Die-to-Die controller IP is available now to early adopters. The Synopsys DesignWare Die-to-Die USR/XSR PHY IP in 12nm, 7nm and 5nm processes are available now with a roadmap to 3nm. The HBI PHY IP in 7nm and 5nm processes are available now.

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