Neural processor IP hits the highs for automotive and data centre designs
Addressing increasing performance requirements for AI SoCs, Synopsys has announced a neural processing unit (NPU) IP and toolchain. The company claims that the DesignWare Arc NPX6 and NPX6FS NPU IP delivers the industry’s highest performance and support for the latest, most complex neural network models.
The Arc NPX6 NPU IP scales from 4K to 96k MACs and delivers, in a single instance, up to 250T operations per second (TOPS) at 1.3GHz on 5nm processes in worst-case conditions. Alternatively, using new sparsity features, it can deliver up to 440 TOPS to increase the performance and decrease energy demands of executing a neural network, says Synopsys.
The IP integrates hardware and software connectivity features that enable implementation of multiple NPU instances to achieve up to 3,500 TOPS of performance on a single SoC and provides more than 50x the performance of the maximum configuration of the earlier Arc EV7x processor IP.
It also offers optional 16-bit floating point support inside the neural processing hardware, to maximise layer performance and simplify the transition from GPUs used for AI prototyping to high volume power- and area-optimised SoCs.
The scalable neural processor has been developed to address the compute and memory demands of AI applications like advanced driver assistance systems (ADAS), surveillance, digital TVs and cameras which implement complex neural network models, often for safety-critical functions.
DesignWare Arc NPX6FS NPU IP meets stringent random hardware fault detection and systematic functional safety development flow requirements to achieve up to ISO 26262 ASIL D compliance. The processors, with comprehensive safety documentation included, feature dedicated safety mechanisms for ISO 26262 compliance and address the mixed-criticality and virtualisation requirements of next-generation zonal architectures.
The IP and toolchain address the demands of real-time compute with low power consumption for AI applications. To accelerate application software development for the ARC NPX6 NPU IP, the company has also introduced the DesignWare Arc MetaWare MX development toolkit for a compilation environment with automatic neural network algorithm partitioning to maximise resource use.
The ARC MetaWare MX development toolkit includes compilers and debugger, neural network software development kit (SDK), virtual platforms SDK, runtimes and libraries, and advanced simulation models. MetaWare MX offers a single toolchain to accelerate application development and automatically partitions algorithms across the MAC resources for highly efficient processing. For safety-critical automotive applications, the MetaWare MX Development Toolkit for Safety includes a safety manual and a safety guide to help developers meet the ISO 26262 requirements and prepare for ISO 26262 compliance testing.
Synopsys’ DesignWare IP portfolio includes logic libraries, embedded memories, IOs, PVT monitors, embedded test, analogue IP, interface IP, security IP, embedded processors and subsystems. To accelerate prototyping, software development and integration of IP into SoCs, Synopsys’ IP Accelerated initiative offers IP prototyping kits, IP software development kits and IP subsystems.
DesignWare ARC NPX6 NPU IP, NPX6FS NPU IP and MetaWare MX Development toolkit are available to lead customers today.