Platform delivers ecosystem of networking-optimised IP
eSilicon has made available a complete, highly configurable 7nm IP platform targeted at networking and data centre applications.
The platform delivers a complete ecosystem of networking-optimised IP with high configurability designed in. All IP in the platform is “plug and play,” using the same metal stack, reliability requirements, operating ranges, control interfaces and DFT methodology.
The platform includes high-performance, flexible 56G and 112G SerDes, a ternary content-addressable memory (TCAM) compiler, a robust and programmable high-bandwidth memory gen2 (HBM2) PHY, multiple network-optimised memory compilers and extended-voltage general-purpose and LVDS I/Os.
Along with eSilicon internally developed IP, the platform is completed with plug-and-play partner IP for functions such as PCI Express PHY, controllers, PLL and PVT monitor.
At the core of the platform is eSilicon’s SerDes technology, a new breed of performance and versatility based on DSP-based architecture. Two 7nm PHYs support 56G and 112G NRZ/PAM4 operation to provide the best power efficiency tradeoffs for server, fabric and line-card applications.
The architecture is said to deliver unprecedented power efficiency for a true long-reach capability, with hole-free operation down to 1 gigabits per second. The clocking architecture provides flexibility to support multi-link and multi-rate operations per SerDes lane.
A variety of protocols are supported including Ethernet and Fibre Channel. The architecture allows scaling power consumption even further for shorter-reach channels.
In addition eSilicon’s SerDes technology provides a new level of usability for the asic design and signal integrity communities. Leveraging a decade of experience integrating complex SerDes into networking asics, eSilicon incorporated this knowledge into its SerDes family.
The current 7nm compiler supports low-power operation with partial-pipelined search. BIST enhancements allow faster design cycles and simulation through soft programming. A patented duo architecture and two-cycle read/write architecture reduce area and power even further for large networking asics.
The HBM2 PHY integrates features to minimise switching noise and duty cycle distortion and as a self-contained, hardened macro offers many programmable hooks to architects.
As well as drive strength calibration for maximum eye opening and jitter reduction plus dedicated circuitry for training and lane repair, eSilicon also offers an 2.5D HBM enablement package. The company says this package
provides easy integration of the HBM2 PHY and associated HBM2 DRAM stacks.
Rounding out the platform is an array of unique, network-optimised, high-speed and ultra-high-density memory compilers, register files and latch-based compilers optimised for extreme density and performance.
Embedded BIST is available as an option to provide optimal DFT coverage, save area on large memories and reduce designers’ efforts in synthesis, timing closure and routing congestion. The platform also includes networking-optimised extended-voltage and LVDS I/Os.