Quartz RFSoC board meets SOSA standard
Designed for communications, electro-optical, electronic warfare radar and signals intelligence applications the Quartz Model 5550 is an eight-channel A/D and D/A converter, 3U OpenVPX board by Pentek. It is based on the Xilinx Zynq UltraScale+ RFSoC and aligned to the Sensor Open Systems Architecture (SOSA) technical standard.
The Model 5550 is ideal for many communications, electro-optical, electronic warfare, radar and signals intelligence applications.
It implements connector technology that enables backplane-only I/O, which is one of the major goals of the SOSA. The board incorporates the ANSI/VITA 67.3D VPX backplane interconnect standard for both coaxial RF and optical I/O. It also includes a 40GigE interface and a shelf-management sub-system, also required in the SOSA.
Pentek adopts a modular approach to hardware and software which enables quick adaptation to new and changing customer requirements. The Model 5550 uses the Model 6001 QuartzXM eXpress module containing the RFSoC FPGA and all support circuitry is implemented on a carrier module designed specifically to align with the technical standard for the SOSA. This allows easy upgrades to third generation RFSoC modules when available, explains Pentek.
The board is pre-loaded with a suite of Pentek IP modules to provide data capture and processing for common applications. Modules include DMA engines, DDR4 memory controller, test signal and metadata generators, data packing and flow control. IP for triggered waveform and radar chirp generation, triggered radar range gate selection, wideband real-time transient capture, flexible multi-mode data acquisition and extended decimation is also pre-installed. For many applications, the Model 5550 can be used immediately with these built-in functions, requiring no FPGA development.
The front end accepts analogue IF or RF inputs on eight coax connectors located within a VITA 67.3D backplane connector. After balun coupling to the RFSoC, the analogue signals are routed to eight 4Gsample per second, 12-bit ADCs. Each converter has built-in digital down converters with programmable 1x, 2x, 4x and 8x decimation and independent tuning. The A/D digital outputs are delivered into the RFSoC programmable logic and processor system for signal processing, data capture or for routing to other resources. A stage of IP based decimation provides another 16x stage of data reduction; this is particularly suitable for applications that need to stream data from all eight A/DCs. Eight 4Gsample per second, 14-bit DACs deliver balun-coupled analogue outputs to a second VITA 67.3D coaxial backplane connector. Four additional 67.3D coaxial backplane connections are provided for clocks and timing signals.
The Model 5550 also uses the VITA-67.3D backplane connector for eight 28Gbit per second duplex optical lanes to the backplane. With two built-in 100GigE UDP interfaces or a user-installed serial protocol in the RFSoC, the VITA-67.3D backplane interface enables gigabit communications independent of the PCIe interface.
Pentek’s Navigator design suite includes Navigator FPGA design kit for custom IP and Navigator board support package for creating host software applications.
