Renesas processors and Winbond memory accelerate AI development

Winbond Electronics has confirmed that its HyperRAM and SpiStack (NOR+NAND) can be operated with Renesas Electronics’ RZ/A2M Arm-based microprocessors to develop flexible AI and imaging processing applications.

Renesas’ RZ/A2M microprocessor is suitable for human machine interface (HMI) applications, especially those with cameras. It supports Mobile Industry Processor Interface (MIPI), the camera interface which is widely used in mobile devices. It is also equipped with a dynamically reconfigurable processor (DRP) for high speed image processing. The RZ/A2M can provide and safe and secure high speed network connection for image recognition in a wide range of applications from consumer electronics to industrial equipment, says Winbond. The RZ/A2M also features two Ethernet channels and it can enhance security functions with a cryptographic hardware accelerator.

Winbond’s HyperRAM is suitable for embedded AI and image processing for classification, in which the electronics circuit needs to be made as small as possible, while providing sufficient storage and data bandwidth to support compute-intensive workloads such as image recognition, explains the company. SpiStack allows designers to store code in the NOR die and data in the NAND die with smallest form factor, claims the company. It can store the boot code and application code for the RZ/A2M on the NOR side while multiple large-sized data, such as learning data for embedded AI and camera images, can be stored on the NAND side.

HyperRAM can operate at a maximum frequency of 200MHz and provide a maximum data transfer rate of 400Mbytes per second with either 3.3 or 1.8V operation voltage. It also offers low power consumption in operating and hybrid sleep modes, says Winbond, citing the 64Mbit HyperRAM standby power consumption of 70 microW at 1.8V at room temperature, and 35 microW consumption at 1.8V in hybrid sleep mode. The 13 signal pins can simplify PCB layout design, says Winbond and allows microprocessors to  have more pins out for other purposes or allows designers to choose microprocessors with fewer pins.

Winbond’s SpiStack (NOR+NAND) is formed by stacking a NOR die and a NAND die into one package, such as a 64Mbit serial NOR with a 1Gbit QspiNAND die. This allows designers the flexibility to store code in the NOR die and data in the NAND die. SpiStack with NOR+NAND has only six signal pins, regardless of the number of stacked dies. The active die is switched by a simple software die selection command (C2h) with a factory-assigned die ID number. The clock rate can be up to 104MHz, an equivalent of 416MHz under quad-SPI, says Winbond. SpiStack (NOR+NAND) also supports concurrent operation, i.e. one of the dies could program/erase while the other die could program/erase/read at the same and vice versa.

Shigeki Kato, vice president of the Enterprise Infrastructure business division at Renesas, said: “As embedded AI systems become more sophisticated and complex, the use of RZ/A2M with external memory can support the increasing data size of application code or trained models”.

Naoki Mimura, general manager of marketing & FAE at Winbond Japan, added: “By adopting Winbond’s HyperRAM and SpiStack (NOR+NAND), it is possible to reduce the mounting area of memory on the PCB, the number of wires, and the BoM cost”.

Both package sizes measure 8.0 x 6.0mm, there are 13 signals for HyperRAM and six signals for SpiStack (NOR+NAND). Compared to conventional SDRAM and parallel NOR/NAND, both of the package size and the number of terminals have been reduced by around 80 per cent, reports Windbond.

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