Run the gamut of RISC-V verification to validation

Imperas Software has partnered with Breker Verification Systems to offer mutual customers a  unified, standards-based approach to verification and verification IP reusability, in the transition between RISC-V processor and system level design verification.

The combined approach to standards-based verification means development teams will be able to efficiently transition from RISC-V processor functional design verification through to system level and SoC integration testing, including automated cache coherency validation, said Imperas.

The company specialises in RISC-V simulation and Breker provides test content synthesis for SoC, UVM and post-silicon verification environments.

The open, standard instruction set architecture (ISA) of RISC-V allows SoC developers to optimise a custom processor for domain specific applications. Using these new RISC-V cores, however, introduces additional system level integration verification challenges, warned Imperas.

Imperas and Breker plan to develop interfaces and standards to unify the functional verification design flows to enable design verification teams to improve efficiency and verification IP reuse across the complete verification process from plan to silicon prototype.

“RISC-V represents an inflection point for semiconductor verification as the design freedoms provided by the open ISA means an assumption of the responsibility of the processor and system verification task,” said David Kelf, CEO at Breker Verification Systems. “In partnering with Imperas. . . we can offer a combination of technologies and interface standards for IP and SoC testing that ensures commercial-grade verification for these flexible devices right through to the end platform.”

“RISC-V marks the end of the one-size-fits-all approach to processor IP, now all SoC developers can explore new innovations with processor IP configured for the target application,” said Simon Davidmann, CEO at Imperas Software. “Many of our customers are exploring the design side possibilities of new processor architectures and their implications for SoCs and systems in parallel, extending the verification scope from IP cores to system level integration. With Breker’s proven system verification experience, we are streamlining the critical verification tasks to enable the full potential of RISC-V based devices with commercial-grade verified quality,” he said.

Both companies will be at the Design Automation conference 2022 (DAC) in San Francisco, California (10 to 14 July). Visit Imperas at booth 2336 and Breker at booth 2528. Both companies are also represented in the OpenHW pavilion (booth 2340). 

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