Scalable DSP architecture increases power and area efficiency
Vector multi-threaded compute technology is used in the Ceva-SC20 DSP architecture by Ceva. This increases power and area efficiency by up to 2.5 times compared to its predecessor
To be launched at next week’s MWC in Barcelona, the fifth generation Ceva-SC DSP architecture is based on a vector multi-threaded massive compute technology that is designed to address 5G-Advanced workloads across smartphones, high-end enhanced mobile broadband (eMBB) devices (e.g. fixed wireless access and industrial terminals) and a range of cellular infrastructure devices (e.g. base stations, virtualised distributed unit (DU) accelerators, and beamforming compute in massive MIMO (multiple input multiple output) radios).
For SoC and ASIC designers, the CEVA-XC20 architecture present the power efficiency to design ‘greener’ processors that are smaller and lower power, said Ceva.
The CEVA-XC20 architecture was designed in consultation with the company’s leading Tier 1 OEM customers, with the common aim of improving mobile network performance and power efficiency. According to Ceva, it solves the performance challenges posed by next-generation compute-intense 5G-Advanced by employing a novel Dynamic Vector Threading (DVT) scheme, which supports true hardware multi-threading, which up until now was only found in general purpose CPU architectures. DVT enables optimal sharing of vector resources between different execution units, for what Ceva describes as an unprecedented vector utilisation efficiency boost. IT achieves optimal utilisation of the VLIW architecture and improves core efficiency for common 5G execution kernels, as well as significantly enhancing use cases involving multi-component carriers and multi-execution tasks. This enables increasing the length of the vector processing units while execution efficiency relative to previous generations.
The first core based on the CEVA-XC20 architecture is the CEVA-XC22 DSP, supporting two execution threads using DVT. The CEVA-XC22 offers a 2.5 fold improvement in efficiency (performance per watt and area) for essential 5G use cases and computation kernels versus its predecessor. The CEVA-XC22 will also be integrated within Ceva’s holistic baseband platforms, PentaG-RAN for cellular infrastructure and PentaG2-Max for high performance mobile devices to power Ceva’s heterogeneous compute platforms, including both DSPs and compute engine accelerators.
The CEVA-XC22 DSP will be available for general licensing in the second quarter of this year.