SerDes IP accelerates cloud hyperscale infrastructure

DSP-based, flex-rate multi-rate SerDes IP is optimised for power, performance, area, for hyperscale ASICs, compute, switching, storage, artificial intelligence / machine learning (AI / ML) and 5G SoCs. Cadence Design Systems has released its third-generation 112G long-reach (112G-LR) SerDes IP on TSMC’s N5 process and claims it offers 25 per cent power improvement, 40 per cent area reduction and better design margins for high-reliability systems, satisfying the increasing needs for higher performance and power efficiency in today’s data centres.

The Cadence 112G-LR PAM4 SerDes IP on TSMC’s N5 process delivers the power, performance and area (PPA) efficiency. N5 test chips are currently undergoing characterisation.

Cadence now offers an enhanced DSP with multiple floating decision feedback equalisation (DFE) taps to enable robust performance. The 1-112G gapless data rate support provides I/O flexibility for chip-to-chip connectivity for AI / ML accelerator SoCs. In addition, a 10-fold improvement in supply noise immunity eases the SoC power delivery network (PDN) design.

The 112G-LR SerDes IP on TSMC’s N5 process is part of the broader Cadence IP portfolio and supports the Cadence Intelligent System Design strategy, which enables advanced-node SoC design excellence.

Cadence has been working closely with early adopter customers on deploying the new 112G-LR SerDes IP in their 5nm SoC development and is ready to engage broadly with customers.

Cadence specialises in electronic design, building on more than 30 years’ of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality. Cadence customers deliver electronic products from chips to boards to systems for the most dynamic market applications, including consumer, hyperscale computing, 5G communications, automotive, mobile, aerospace, industrial and healthcare.

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