Silicon Labs expands timing portfolio
To meet the high-performance clocking requirements of 56G PAM-4 SerDes and emerging 112G serial applications, Silicon Labs has added to its timing portfolio.
The company now offers a comprehensive selection of clock generators, jitter attenuating clocks, voltage-controlled crystal oscillators (VCXOs) and XOs for 100/200/400/600G designs that satisfy sub-100 fs reference clock jitter requirements with margin. It is claimed to be the first timing supplier to provide fully integrated clock IC solutions for 56G designs that integrate SerDes, CPU and system clocks into a single device.
The new clock and oscillator products meet current 56G SerDes requirements, as well as the needs of emerging 112G serial SerDes designs that will ramp in data centre and communications applications in the future.
timing solutions to meet their 56G SerDes application needs.”
The Si5391 provides all clock frequencies needed in 200/400/600G designs from a single IC while delivering sub-100 fs RMS phase jitter performance for 56G SerDes reference clocks.
Featuring up to 12 differential outputs, the Si5391 clock is available in frequency flexible A/B/C/D grade options. A precision calibration P-grade option optimises RMS phase jitter performance with a 69 fs (typical) specification for the primary frequencies needed in 56G SerDes designs.
The Si5391 is a true sub-100 fs “clock tree on a chip” solution designed to synthesise all output frequencies from the same IC while meeting 56G PAM-4 reference clock jitter requirements with margin.
Designed to meet the exacting specifications and high-performance requirements of Internet infrastructure, these ultra-low jitter clocks generate any combination of output frequencies from any input frequency while delivering 90 fs RMS phase jitter. Si5395/4/2 P-grade devices offer best-in-class jitter (69 fs RMS typical phase jitter) for 56G/112G SerDes clocking applications.
The new Si56x Ultra Series VCXO and XO family suits next-generation high-performance timing applications requiring ultra-low jitter oscillators. Si56x VCXO/XOs are customisable to any frequency up to 3 GHz, supporting twice the operating frequency range of previous Silicon Labs VCXO products with half the jitter.
These oscillators are available with single, dual, quad, and I2C-programmable options in industry-standard 5 mm x 7 mm and 3.2 mm x 5 mm packages, enabling drop-in compatibility with traditional XO, VCXOs and VCSOs. This family features devices with typical phase jitter down to 90 fs.
Silicon Labs also offers the Si54x Ultra Series XO family for applications requiring tighter stability and guaranteed long-term reliability, such as optical transport networking (OTN), broadband equipment, data centres and industrial systems.
The Si54x XOs are purpose-built for 56G designs, which rely on four-level pulse-amplitude modulation (PAM-4) signalling for serial data transmission to increase the bit rate per channel while keeping the bandwidth constant.
Using an Si54x XO as a low-jitter reference clock maximizes signal-to-noise ratio (SNR) headroom, minimises bit errors and enhances signal integrity.
The Si54x family offers best-in-class performance, with typical phase jitter down to 80 fs.
