Single vendor validation supports PCIe 5.0 and 6.0
To complete design cycle deployments in peripheral component interconnect express (PCIe) testing, Keysight Technologies has introduced a PCIe test system which enables digital development and senior engineers to test simulation, pathfinding, characterisation, validation and compliance testing of PCIe designs.
The rapid increase of AI-related workloads in data centres and edge computing require higher speed devices within reduced design cycles. New PCIe devices will need to keep up with Ethernet network interfaces in data centres and the emergence of CXL (compute express link), explains Keysight.
To maintain performance goals and prepare for the PCIe 6.0 move to pulse amplitude modulation 4-level (PAM4), customers need a smooth transition from PCIe 5.0 to 6.0, where the integrity of PCIe measurements are backed by tools and comply with PCIe specifications. Shrinking design cycles require end-to-end solutions from simulation to validation through the layers of the stack.
Keysight’s physical layer test solution is approved by the Peripheral Component Interconnect Special Interest Group (PCI-SIG) to test transmitters and receivers for all generations of the PCIe specification. To reflect the increasing time to market pressure for design engineers, Keysight extends the portfolio to cover PCIe protocol, making it the first end-to-end solution from simulation to full stack validation, says the company.
The PCIe test solution leverages the company’s physical layer-system simulation, physical layer interconnect, transmitter (Tx) and receiver (Rx) test and a new protocol layer test consisting of hardware and software products. It offers interoperability and support across the entire design cycle. The Keysight Infiniium UXR-Series real time oscilloscope takes PAM4 PCIe 6.0 Tx measurements and Rx calibrations to enable low intrinsic noise. The 110GHz bandwidth provides future proof capabilities, says Keysight.
There is also the M8040A bit error ratio tester (BERT), which uses the same hardware for non-return to zero (NRZ) and PAM-4 measurements. The PCIe test also includes signal integrity that enables engineers to focus on protocol bugs rather than interposer signalling issues and fast transmitter phased locked loop (PLL) bandwidth measurements to reduce the measurement time from hours to seconds.
There is also end-to-end verification of components and sub-systems across the product workflow with common software platforms and built-in test automation capabilities.
