Software offers modelling and simulation for high speed digital designs
PathWave Advanced Design System (ADS) 2023 software offers modelling and simulation of next generation memory standards, said Keysight Technologies. The software has new Memory Designer capabilities for modelling and simulation of next generation interface standards such as Double Data Rate 5 (DDR5).
The need for DDR DRAM and other high density, fast memories is a result of data centre throughput increasing together with advances in servers and high performance computing.
Keysight’s PathWave ADS 2023 ensures rapid simulation set up and advanced measurements and provides critical insights to overcome signal integrity challenges. The Memory Designer constructs parameterised memory buses using the new pre-layout builder. This allows designers to explore system trade-offs that reduce design time and de-risk product development for DDR5, low power double data rate (LPDDR5 / 5x) and graphics DDR (GDDR6 / 7) memory systems.
Lorenzo Forni, PCB design and SI/PI leader at SECO, which designs and produces embedded systems, explained that stack-up analysis, routing geometry and the AMI models must be stacked and that the Memory Designer for the DDR5 simulation is automated. “The configurations are built-in and it’s very easy. The set up of the Memory Designer schematic reduced the amount of time needed, and simulation caught many issues during our design process,” he said.
Keysight’s PathWave ADS 2023 key customer benefits include accurate simulation and modelling and supports LPDDR4, LPDDR5, GDDR6, GDDR7, HBM2/2E, HBM3, and NAND. It also predicts the closure and equalisation of the data eye to minimise the impact of jitter, ISI and crosstalk using single-ended I/O buffer information specification algorithmic modelling interface (IBIS-AMI) modelling with forwarded clocking, DDR bus simulation and electromagnetic extraction of PCB signal routing.
The single design environment shortens time-to-market, enabling pathfinding in pre-silicon digital twins to address current integration requirements such as forwarded clocking and timing, IBIS-AMI modelling and compliance tests and future challenges like single-ended pulse amplitude modulation 4 level (PAM4), for exploration of DDR6.
The software generates buses via a parameterised pre-layout builder which enables designers to quickly generate wide buses of memory signals and easily create flexible schematics to explore trade-offs.
Simulation is completed up to 80 per cent faster with cloud-based HPC, using parallel processing to accelerate Memory Designer and EM simulation run times, said Keysight Technologies.
The software automates design-to-test workflows with a connection between simulation and measurement domains to enable comparison of the stored data against measured results from physical prototypes.