Synopsys claims industry’s first CXL IP for data-intensive SoCs

Low latency and high bandwidth are assured for artificial intelligence (AI), memory expansion and cloud computing, says Synopsys at the introduction of its DesignWare Compute Express Link (CXL) IP.

It is, according to Synopsys, the industry’s first CXL IP for data-intensive system of chips (SoCs). The IP suite consists of controller, PHY, and verification IP for AI, memory expansion, and high-end cloud computing system-on-chips (SoCs). The CXL protocol enables low-latency data communication between the SoC and general-purpose accelerators, memory expanders, and smart I/O devices requiring high-performance, heterogenous computing for data-intensive workloads. The DesignWare CXL IP is compliant with the CXL 1.1 specification and supports all three CXL protocols (, CXL.cache, CXL.mem) and device types to meet specific application requirements.

The CXL IP is built on Synopsys’ DesignWare IP for PCI Express 5.0, which has been adopted by semiconductor companies across all key market segments, reports the company.

“Compute Express Link is a key enabler for next-generation heterogeneous computing architectures, where CPUs and accelerators work together to deliver the most advanced solutions,” said Dr. Debendra Das Sharma, Intel Fellow and director of I/O Technology and Standards at Intel.

Synopsys’ DesignWare CXL Controller helps designers achieve timing closure at 1GHz and provides a robust 512-bit architecture that supports x16 links for maximum CXL bandwidth. The CXL controller offers reliability, availability, serviceability (RAS) capabilities to help maintain data reliability, as well as successfully debug and resolve linkup issues. The 32GTerabytes per second PHY allows more than 36dB channel loss across power, voltage and temperature (PVT) variations for long-reach applications. The VC Verification IP for CXL verifies I/O, memory access, and coherency protocol features with built-in sequences, checks, and coverage for all link configurations up to 16 lanes and 32GTbytes per second data rates. SystemVerilog test suites for CXL accelerate verification closure and are available as source code.

Synopsys’ 32G PHY IP for CXL is available now in 16-, 10-, and 7nm FinFET processes. The CXL Controller and VC Verification IP for CXL are available now.

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