Synopsys introduces native automotive tools for ADAS SoCs

To accelerate automotive SoC design, Synopsys has introduced native automotive design tools to satisfy higher automotive safety integrity levels (ASILs) for autonomous driving and advanced driver-assistance systems (ADAS).

The tools are claimed to provide the industry’s most comprehensive feature set to implement functional safety (FuSa) mechanisms, such as triple-mode redundancy (TMR), dual-core lock-step (DCLS) and failsafe finite state machine (FSM) to achieve target ASILs.

Synopsys’ comprehensive automotive design solutions deliver complex FuSa analysis, implementation, and verification capabilities. Differentiated offerings for automotive design, such as unified functional safety verification and native automotive solutions, enable designers to prove at the planning and implementation phases that their chip safety architecture can achieve target ASILs.

Designers can generate the industry’s first FuSa intent early in the design flow to describe safety mechanism behaviour, says Synopsys. FuSa intent is used as input and maintained throughout the digital design flow. Synopsys’ digital design flow incorporate FuSa-enabled technologies, which work together to maximise efficiency. One is TestMAX FuSa which performs early functional-safety analysis at RTL- or gate-level and identifies candidates for TMR or DCLS redundancy to achieve single-point fault metric (SPFM) goals for target ASIL. There is also Design Compiler NXT synthesis, IC Compiler II place-and-route and Fusion Compiler to design insert, check and report the safety mechanisms implemented. Another technology is the Formality equivalence checker which functionally verifies that the RTL matches the netlist after redundancy or additional logic modules are inserted. Finally, there is the IC Validator physical signoff which verifies the layout and reports that all redundancy mechanisms are correctly implemented.

According to Shankar Krishnamoorthy, senior vice president of design implementation for the Design Group at Synopsys, the company “now offers the industry’s first complete set of natively integrated capabilities to implement and verify functional safety mechanisms. Designers will benefit from significantly reduced time-to-market and improved quality-of-results for their safety-critical automotive designs.”

Synopsys also provides complete solutions to address reliability challenges, including electromigration (EM), voltage (IR) drop, device aging, and robust redundant via insertion (RVI) capabilities. Synopsys provides designers with a broad portfolio of automotive IP that is designed and tested for AEC-Q100 reliability, offers ASIL-ready ISO 26262 certification, and supports automotive quality management.

Synopsys’ unified functional safety verification includes VC Functional Safety Manager, a high-quality, scalable, and distributed FMEDA automation tool,  the Z01X fault simulator, VC Formal FuSa App, TestMAX CustomFault fault simulator for analogue and mixed-signal fault simulation for full-chip functional safety and test coverage analysis, the ZeBu emulator, Verdi Fault Analysis and Certitude functional qualification to demonstrate verification flow robustness in support of ISO 26262 Part 8-9 assessments.

The native automotive tools will be generally available in December 2019.

Latest News from Softei

This news story is brought to you by, the specialist site dedicated to delivering information about what’s new in the electronics industry, with daily news updates, new products and industry news. To stay up-to-date, register to receive our weekly newsletters and keep yourself informed on the latest technology news and new products from around the globe. Simply click this link to register here: Softei Registration