Synopsys, TSMC and Microsoft Azure partner to reduce chip turnaround time
Throughput gains described as “significant” are claimed for signoff and extraction rates for chip design, as a result of a collaboration between Synopsys, TSMC and Microsoft.
The partners have published details of speeding up the path to signoff next-generation SoCs, with a flow that improves throughput using Synopsys PrimeTime static timing analysis and StaRC parasitic extraction on the Microsoft Azure platform.
Design signoff challenges for today’s designs include increased complexity due to advanced process technologies, larger library size, and higher number of operating conditions to analyse. Suk Lee, senior director of the Design Infrastructure Management Division at TSMC, explained: “Utilising a cloud platform offers a great way to accelerate signoff significantly and will fundamentally influence silicon design. TSMC is the first foundry to collaborate with design ecosystem partners and cloud providers to enable design in the cloud. Working with Microsoft and Synopsys, our cloud alliance has demonstrated remarkable throughput improvement and scalability of timing signoff and offers a flexible, secure and efficient way for our mutual customers to accelerate time to market for their SoCs.”
Mujtaba Hamid, head of product management, Silicon, Electronics and Gaming at Microsoft Azure, added: “At advanced nodes, reducing design time requires technology innovation across the infrastructure and tool chain due to high process complexity. This collaboration provides key insights into trade offs involved between cost and performance for these signoff iterations, thus helping the customers make effective decisions for the design of their silicon products.”
On a multi-million gate design using the TSMC N5 process, PrimeTime static timing analysis and StarRC extraction, timing signoff was performed on Microsoft Azure’s latest Edsv4-series compute instances. PrimeTime DMSA and StarRC multi-corner extraction scale-out saw significant throughput gains by massively parallelising the runs over hundreds of machines. Additionally, scaling-in showed major cost savings by running multiple scenarios on a single machine.
Jacob Avidan, senior vice president of Design Signoff in the Design Group at Synopsys, added: “With the industry-leading and TSMC-certified PrimeTime and StarRC solutions on Microsoft Azure, our customers can leverage the cloud to signoff their chips with significantly higher throughput while meeting their PPA targets with TSMC’s latest advanced process technologies.”
Synopsys develops electronic products and software applications and is the world’s 15th largest software company. It has expertise in electronic design automation (EDA) and semiconductor IP and is also growing its leadership in software security and quality solutions. Its products are used by soC designers creating advanced semiconductors and software developers writing applications that require the highest security and quality.
